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/external/valgrind/docs/internals/
D3_9_BUGSTATUS.txt5 === VEX/amd64 ==========================================================
15 330590 Missing support for multiple VEX CMP instruction Opcodes (Causes SIGILL)
22 === VEX/arm ============================================================
31 === VEX/arm64 ==========================================================
36 === VEX/x86 ============================================================
41 === VEX/mips ===========================================================
43 === VEX/ppc ============================================================
47 === VEX general ========================================================
176 338252 CFLAGS="-flto" and VEX/pub/libvex_guest_offsets.h (wishlist)
D3_10_BUGSTATUS.txt5 === VEX/amd64 ==========================================================
20 === VEX/arm ============================================================
34 === VEX/arm64 ==========================================================
36 === VEX/x86 ============================================================
63 === VEX/mips ===========================================================
70 === VEX/ppc ============================================================
74 === VEX/s390x ==========================================================
76 === VEX general ========================================================
D3_11_BUGSTATUS.txt6 === VEX/amd64 ==========================================================
11 360415 amd64 instructions ADCX and ADOX are not implemented in VEX
26 === VEX/arm ============================================================
40 === VEX/arm64 ==========================================================
42 === VEX/x86 ============================================================
44 === VEX/mips ===========================================================
46 === VEX/ppc ============================================================
50 === VEX/s390x ==========================================================
55 === VEX general ========================================================
401 3261 -> 3268 mips: allow VEX to be compiled for soft-float
D3_12_BUGSTATUS.txt6 === VEX/amd64 ==========================================================
36 === VEX/arm ============================================================
62 === VEX/arm64 ==========================================================
68 === VEX/x86 ============================================================
70 === VEX/mips ===========================================================
72 === VEX/ppc ============================================================
77 === VEX/s390x ==========================================================
83 === VEX general ========================================================
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td356 def VMOVSSrm : sse12_move_rm<FR32, f32mem, loadf32, "movss">, XS, VEX,
359 def VMOVSDrm : sse12_move_rm<FR64, f64mem, loadf64, "movsd">, XD, VEX,
365 [(store FR32:$src, addr:$dst)]>, XS, VEX, VEX_LIG;
368 [(store FR64:$src, addr:$dst)]>, XD, VEX, VEX_LIG;
667 "movaps", SSEPackedSingle>, TB, VEX;
669 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
671 "movups", SSEPackedSingle>, TB, VEX;
673 "movupd", SSEPackedDouble, 0>, TB, OpSize, VEX;
676 "movaps", SSEPackedSingle>, TB, VEX;
678 "movapd", SSEPackedDouble>, TB, OpSize, VEX;
[all …]
DX86InstrFormats.td111 class VEX { bit hasVEXPrefix = 1; }
113 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
148 bit hasVEXPrefix = 0; // Does this inst require a VEX prefix?
150 bit hasVEX_4VPrefix = 0; // Does this inst require the VEX.VVVV field?
261 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
272 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
283 let Predicates = !if(hasVEXPrefix /* VEX */, [HasAVX],
294 let Predicates = !if(hasVEX_4VPrefix /* VEX */, [HasAVX],
/external/valgrind/memcheck/tests/vbit-test/
DMakefile.am39 -I$(top_srcdir)/VEX/pub
42 vbit_test_LDADD = $(top_builddir)/VEX/libvex-@VGCONF_ARCH_PRI@-@VGCONF_OS@.a
DREADME33 To get the IRICB to VEX we use the new client request
56 typeof_primop which were imported from VEX/priv/ir_defs.c.
76 <valgrind>/VEX/priv/ir_inject.c
/external/llvm/test/TableGen/
Ddefmclass.td7 class VEX { bit hasVEX_4VPrefix = 1; }
38 defm Instr : Y, VEX;
/external/swiftshader/third_party/LLVM/test/TableGen/
Ddefmclass.td7 class VEX { bit hasVEX_4VPrefix = 1; }
38 defm Instr : Y, VEX;
/external/valgrind/solaris/
Dbuild_solaris_package64 svn export --quiet --ignore-externals $source_directory/VEX $SRCDIR/VEX \
72 vex_rev=$( svn info $source_directory/VEX | grep Revision | sed -e 's/Revision: //' )
/external/llvm/lib/Target/X86/
DX86InstrSSE.td541 VEX, VEX_LIG, Sched<[WriteStore]>;
561 IIC_SSE_MOV_S_RM, d>, VEX, VEX_LIG, Sched<[WriteLoad]>;
760 // Aliases to help the assembler pick two byte VEX encodings by swapping the
761 // operands relative to the normal instructions to use VEX.R instead of VEX.B.
790 PS, VEX;
793 PD, VEX;
796 PS, VEX;
799 PD, VEX;
803 PS, VEX, VEX_L;
806 PD, VEX, VEX_L;
[all …]
/external/valgrind/
DMakefile.tool-tests.am7 -I$(top_srcdir)/VEX/pub \
8 -I$(top_builddir)/VEX/pub \
DMakefile.all.am154 -I$(top_srcdir)/VEX/pub \
155 -I$(top_builddir)/VEX/pub \
165 -I$(top_srcdir)/VEX/pub \
166 -I$(top_builddir)/VEX/pub \
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/X86/
Dinvalid-VEX-vvvv.txt3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
/external/llvm/test/MC/Disassembler/X86/
Dinvalid-VEX-vvvv.txt3 # This instruction would decode as movmskps if the vvvv field in the VEX prefix was all 1s.
/external/valgrind/none/tests/amd64/
Dfma4.vgtest3 # But since VEX just uses AVX instructions to implement the fma4 one, just
/external/valgrind/memcheck/tests/common/
DMakefile.in371 -I$(top_srcdir)/VEX/pub \
372 -I$(top_builddir)/VEX/pub \
382 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
383 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
504 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/gdbserver_tests/solaris/
DMakefile.in374 -I$(top_srcdir)/VEX/pub \
375 -I$(top_builddir)/VEX/pub \
385 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
386 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
507 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/none/tests/scripts/
DMakefile.in374 -I$(top_srcdir)/VEX/pub \
375 -I$(top_builddir)/VEX/pub \
385 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
386 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
507 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/exp-bbv/tests/x86-linux/
DMakefile.in421 -I$(top_srcdir)/VEX/pub \
422 -I$(top_builddir)/VEX/pub \
432 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
433 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
554 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/exp-bbv/tests/ppc32-linux/
DMakefile.in421 -I$(top_srcdir)/VEX/pub \
422 -I$(top_builddir)/VEX/pub \
432 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
433 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
554 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/exp-bbv/tests/
DMakefile.in441 -I$(top_srcdir)/VEX/pub \
442 -I$(top_builddir)/VEX/pub \
452 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
453 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
574 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/exp-bbv/tests/arm-linux/
DMakefile.in421 -I$(top_srcdir)/VEX/pub \
422 -I$(top_builddir)/VEX/pub \
432 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
433 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
554 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \
/external/valgrind/memcheck/tests/arm64-linux/
DMakefile.in414 -I$(top_srcdir)/VEX/pub \
415 -I$(top_builddir)/VEX/pub \
425 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_srcdir)/VEX/pub \
426 @VGCONF_HAVE_PLATFORM_SEC_TRUE@ -I$(top_builddir)/VEX/pub \
547 -I$(top_srcdir)/VEX/pub -I$(top_builddir)/VEX/pub \

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