Home
last modified time | relevance | path

Searched refs:VFP (Results 1 – 25 of 70) sorted by relevance

123

/external/llvm/test/MC/ARM/
Dvfp-aliases-diagnostics.s34 @ CHECK: error: VFP/Neon double precision register expected
37 @ CHECK: error: VFP/Neon double precision register expected
40 @ CHECK: error: VFP/Neon double precision register expected
43 @ CHECK: error: VFP/Neon double precision register expected
46 @ CHECK: error: VFP/Neon single precision register expected
49 @ CHECK: error: VFP/Neon single precision register expected
52 @ CHECK: error: VFP/Neon single precision register expected
55 @ CHECK: error: VFP/Neon single precision register expected
59 @ CHECK: error: VFP/Neon single precision register expected
62 @ CHECK: error: VFP/Neon single precision register expected
[all …]
Dsingle-precision-fp.s10 @ CHECK-ERRORS: error: instruction requires: double precision VFP
12 @ CHECK-ERRORS: error: instruction requires: double precision VFP
14 @ CHECK-ERRORS: error: instruction requires: double precision VFP
16 @ CHECK-ERRORS: error: instruction requires: double precision VFP
18 @ CHECK-ERRORS: error: instruction requires: double precision VFP
29 @ CHECK-ERRORS: error: instruction requires: double precision VFP
31 @ CHECK-ERRORS: error: instruction requires: double precision VFP
33 @ CHECK-ERRORS: error: instruction requires: double precision VFP
35 @ CHECK-ERRORS: error: instruction requires: double precision VFP
37 @ CHECK-ERRORS: error: instruction requires: double precision VFP
[all …]
Dneon-mov-vfp.s1 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
2 …nknown -show-encoding -mattr=-neon < %s 2>&1 | FileCheck %s --check-prefix=VFP --check-prefix=CHECK
14 @ VFP-DAG: error: instruction requires: NEON
15 @ VFP-DAG: error: instruction requires: NEON
26 @ VFP-DAG: error: instruction requires: NEON
27 @ VFP-DAG: error: instruction requires: NEON
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfpconv.ll1 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
5 ;CHECK-VFP: f1:
6 ;CHECK-VFP: vcvt.f32.f64
15 ;CHECK-VFP: f2:
16 ;CHECK-VFP: vcvt.f64.f32
25 ;CHECK-VFP: f3:
26 ;CHECK-VFP: vcvt.s32.f32
35 ;CHECK-VFP: f4:
36 ;CHECK-VFP: vcvt.u32.f32
45 ;CHECK-VFP: f5:
[all …]
Dselect.ll2 ; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s --check-prefix=CHECK-VFP
63 ;CHECK-VFP: f7:
64 ;CHECK-VFP: vmovmi
98 ; CHECK-VFP: f9:
/external/llvm/test/CodeGen/ARM/
Dfpconv.ll1 ; RUN: llc -mtriple=arm-eabi -mattr=+vfp2 %s -o - | FileCheck %s --check-prefix=CHECK-VFP
5 ;CHECK-VFP-LABEL: f1:
6 ;CHECK-VFP: vcvt.f32.f64
15 ;CHECK-VFP-LABEL: f2:
16 ;CHECK-VFP: vcvt.f64.f32
25 ;CHECK-VFP-LABEL: f3:
26 ;CHECK-VFP: vcvt.s32.f32
35 ;CHECK-VFP-LABEL: f4:
36 ;CHECK-VFP: vcvt.u32.f32
45 ;CHECK-VFP-LABEL: f5:
[all …]
Dfp16-promote.ll1 …=+vfp3,+fp16 | FileCheck %s -check-prefix=CHECK-FP16 --check-prefix=CHECK-VFP -check-prefix=CHECK…
2 …eck-prefix=CHECK-LIBCALL --check-prefix=CHECK-VFP -check-prefix=CHECK-ALL --check-prefix=CHECK-LIB…
13 ; CHECK-VFP: vadd.f32
30 ; CHECK-VFP: vsub.f32
47 ; CHECK-VFP: vmul.f32
64 ; CHECK-VFP: vdiv.f32
122 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
123 ; CHECK-VFP-NEXT: vmov.f32 s0, s1
124 ; CHECK-VFP-NEXT: vmov.f32 s1, s2
137 ; CHECK-VFP-NEXT: vmov.f32 s2, s0
[all …]
Dno-fpu.ll4 …N: llc < %s -mtriple=armv7-none-gnueabi -mattr=-neon,+vfp2 | FileCheck --check-prefix=NONEON-VFP %s
22 ; Likewise with VFP instructions.
29 ; NONEON-VFP: vmov
30 ; NONEON-VFP: vmul.f64
Dselect.ll4 ; RUN: | FileCheck %s --check-prefix=CHECK-VFP
67 ;CHECK-VFP-LABEL: f7:
68 ;CHECK-VFP: vmovmi
101 ; CHECK-VFP-LABEL: f9:
D2013-04-16-AAPCS-C5-vs-VFP.ll7 ;Co-Processor register candidates may be either in VFP or in stack, so after
8 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
Dvector-extend-narrow.ll23 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
52 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
D2013-04-16-AAPCS-C4-vs-VFP.ll6 ;Co-Processor register candidates may be either in VFP or in stack, so after
7 ;all VFP are allocated, stack is used. We can use stack without GPR allocation
D2013-04-21-AAPCS-VA-C.1.cp.ll2 ;Note: There are no VFP CPRCs in a variadic procedure.
Dvfp-regs-dwarf.ll10 ; the layout of the VFP registers correctly. The fact that the numbers are
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrVFP.td1 //===- ARMInstrVFP.td - VFP support for ARM ----------------*- tablegen -*-===//
10 // This file describes the ARM VFP instruction set.
78 // Some single precision VFP instructions may be executed on both NEON and VFP
92 // Some single precision VFP instructions may be executed on both NEON and VFP
140 // Some single precision VFP instructions may be executed on both NEON and
141 // VFP pipelines.
153 // Some single precision VFP instructions may be executed on both NEON and
154 // VFP pipelines.
166 // Some single precision VFP instructions may be executed on both NEON and
167 // VFP pipelines.
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrVFP.td1 //===-- ARMInstrVFP.td - VFP support for ARM ---------------*- tablegen -*-===//
10 // This file describes the ARM VFP instruction set.
108 // Some single precision VFP instructions may be executed on both NEON and VFP
127 // Some single precision VFP instructions may be executed on both NEON and VFP
180 // Some single precision VFP instructions may be executed on both NEON and
181 // VFP pipelines.
193 // Some single precision VFP instructions may be executed on both NEON and
194 // VFP pipelines.
206 // Some single precision VFP instructions may be executed on both NEON and
207 // VFP pipelines.
[all …]
DARM.td104 // Cyclone has preferred instructions for zeroing VFP registers, which can
153 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
155 "Expand VFP/NEON MLA/MLS instructions">;
157 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
162 // VFP to NEON, as an execution domain optimization.
179 // Some processors have a nonpipelined VFP coprocessor.
182 "VFP instructions are not pipelined">;
185 // play nicely with other VFP / NEON instructions, and it's generally better
188 "Disable VFP / NEON MAC instructions">;
DARMScheduleSwift.td586 // 4.2.34 Advanced SIMD and VFP, Floating Point
596 // 4.2.35 Advanced SIMD and VFP, Multiply
608 // 4.2.36 Advanced SIMD and VFP, Convert
613 // 4.2.37 Advanced SIMD and VFP, Move
640 // 4.2.38 Advanced SIMD and VFP, Move FPSCR
661 // 4.2.39 Advanced SIMD and VFP, Load Single Element
664 // 4.2.40 Advanced SIMD and VFP, Store Single Element
667 // 4.2.41 Advanced SIMD and VFP, Load Multiple
668 // 4.2.42 Advanced SIMD and VFP, Store Multiple
1025 // 4.2.44 VFP, Divide and Square Root
/external/vixl/src/aarch32/
Doperands-aarch32.h538 if (VFP::IsImmFP32(imm)) { in ImmediateVFP()
539 SetEncodingValue(VFP::FP32ToImm8(imm)); in ImmediateVFP()
543 if (VFP::IsImmFP64(imm)) { in ImmediateVFP()
544 SetEncodingValue(VFP::FP32ToImm8(imm)); in ImmediateVFP()
555 return VFP::Imm8ToFP32(imm8); in Decode()
559 return VFP::Imm8ToFP64(imm8); in Decode()
/external/elfutils/tests/
Drun-readelf-A.sh51 ABI_VFP_args: VFP registers
/external/llvm/test/CodeGen/Thumb2/
Dfloat-intrinsics-float.ll3 …k %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-A…
123 ; VFP: lsrs [[REG:r[0-9]+]], r{{[0-9]+}}, #31
124 ; VFP: bfi r{{[0-9]+}}, [[REG]], #31, #1
Dfloat-intrinsics-double.ll3 …k %s -check-prefix=CHECK -check-prefix=HARD -check-prefix=DP -check-prefix=VFP -check-prefix=FP-A…
128 ; VFP: lsrs [[REG:r[0-9]+]], r3, #31
129 ; VFP: bfi r1, [[REG]], #31, #1
/external/python/cpython2/Modules/_ctypes/libffi/src/arm/
Dsysv.S343 @ Make room for loading VFP args
349 sub r2, fp, #64 @ VFP scratch space
354 @ Load VFP register args if needed
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DSplitKit.cpp383 ValueForcePair &VFP = Values[std::make_pair(RegIdx, ParentVNI->id)]; in forceRecompute() local
384 VNInfo *VNI = VFP.getPointer(); in forceRecompute()
389 VFP.setInt(true); in forceRecompute()
398 VFP = ValueForcePair(0, true); in forceRecompute()
836 ValueForcePair VFP = Values.lookup(std::make_pair(RegIdx, ParentVNI->id)); in transferValues() local
837 if (VNInfo *VNI = VFP.getPointer()) { in transferValues()
845 if (VFP.getInt()) { in transferValues()
/external/libunwind_llvm/src/
DUnwindRegistersSave.S306 @ however this is very hard to do for VFP registers because it is unknown
308 @ Instead, VFP registers are demand saved by logic external to unw_getcontext.
375 @ VFP and iwMMX instructions are only available when compiling with the flags

123