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Searched refs:VLD3DUP (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h192 VLD3DUP, enumerator
DARMInstrNEON.td992 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
993 class VLD3DUP<bits<4> op7_4, string Dt>
1002 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1003 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1004 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1011 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1012 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1013 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
DARMISelLowering.cpp923 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
7215 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
7301 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
7956 case ARMISD::VLD3DUP: in PerformDAGCombine()
DARMISelDAGToDAG.cpp2723 case ARMISD::VLD3DUP: { in Select()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h194 VLD3DUP, enumerator
DARMInstrNEON.td1515 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1516 class VLD3DUP<bits<4> op7_4, string Dt>
1525 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1526 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1527 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1534 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1535 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1536 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
DARMISelLowering.cpp1228 case ARMISD::VLD3DUP: return "ARMISD::VLD3DUP"; in getTargetNodeName()
9962 case ARMISD::VLD3DUP: NewOpc = ARMISD::VLD3DUP_UPD; NumVecs = 3; break; in CombineBaseUpdate()
10131 NewOpc = ARMISD::VLD3DUP; in CombineVLDDUP()
11065 case ARMISD::VLD3DUP: in PerformDAGCombine()
DARMISelDAGToDAG.cpp3155 case ARMISD::VLD3DUP: { in Select()