| /external/libhevc/common/arm/ |
| D | ihevc_sao_edge_offset_class1_chroma.s | 187 VUZP.8 D12,D13
202 VUZP.8 D22,D23
258 VUZP.8 D22,D23
337 VUZP.8 D12,D13
355 VUZP.8 D22,D23
394 VUZP.8 D22,D23
|
| D | ihevc_sao_edge_offset_class0_chroma.s | 222 VUZP.8 D14,D15
242 VUZP.8 D24,D25 @II
387 VUZP.8 D14,D15
409 VUZP.8 D28,D29 @II
|
| D | ihevc_sao_edge_offset_class3_chroma.s | 420 VUZP.8 D18,D19 @I
533 VUZP.8 D26,D27 @II
558 VUZP.8 D18,D19 @III
651 VUZP.8 D18,D19
828 VUZP.8 D26,D27
1002 VUZP.8 D26,D27
|
| D | ihevc_sao_edge_offset_class2_chroma.s | 430 VUZP.8 D22,D23 @I
531 VUZP.8 D26,D27 @II
565 VUZP.8 D18,D19 @III
651 VUZP.8 D26,D27
804 VUZP.8 D26,D27
952 VUZP.8 D26,D27
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vuzp.ll | 27 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
77 ; Undef shuffle indices should not prevent matching to VUZP:
|
| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 177 VUZP.8 D2,D3
314 VUZP.8 D2,D3
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon.txt | 3527 VUZP/VUZPQ chunk 0 output:
3528 VUZP/VUZPQ:0:result_int8x8 [] = { fffffff0, fffffff1, fffffff2, fffffff3, fffffff4, fffffff5, fffff…
3529 VUZP/VUZPQ:1:result_int16x4 [] = { fffffff0, fffffff1, fffffff2, fffffff3, }
3530 VUZP/VUZPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3531 VUZP/VUZPQ:3:result_int64x1 [] = { 3333333333333333, }
3532 VUZP/VUZPQ:4:result_uint8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
3533 VUZP/VUZPQ:5:result_uint16x4 [] = { fff0, fff1, fff2, fff3, }
3534 VUZP/VUZPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3535 VUZP/VUZPQ:7:result_uint64x1 [] = { 3333333333333333, }
3536 VUZP/VUZPQ:8:result_poly8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
[all …]
|
| D | ref-rvct-neon-nofp16.txt | 3311 VUZP/VUZPQ chunk 0 output:
3312 VUZP/VUZPQ:0:result_int8x8 [] = { fffffff0, fffffff1, fffffff2, fffffff3, fffffff4, fffffff5, fffff…
3313 VUZP/VUZPQ:1:result_int16x4 [] = { fffffff0, fffffff1, fffffff2, fffffff3, }
3314 VUZP/VUZPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3315 VUZP/VUZPQ:3:result_int64x1 [] = { 3333333333333333, }
3316 VUZP/VUZPQ:4:result_uint8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
3317 VUZP/VUZPQ:5:result_uint16x4 [] = { fff0, fff1, fff2, fff3, }
3318 VUZP/VUZPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3319 VUZP/VUZPQ:7:result_uint64x1 [] = { 3333333333333333, }
3320 VUZP/VUZPQ:8:result_poly8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
[all …]
|
| D | ref-rvct-all.txt | 3527 VUZP/VUZPQ chunk 0 output:
3528 VUZP/VUZPQ:0:result_int8x8 [] = { fffffff0, fffffff1, fffffff2, fffffff3, fffffff4, fffffff5, fffff…
3529 VUZP/VUZPQ:1:result_int16x4 [] = { fffffff0, fffffff1, fffffff2, fffffff3, }
3530 VUZP/VUZPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3531 VUZP/VUZPQ:3:result_int64x1 [] = { 3333333333333333, }
3532 VUZP/VUZPQ:4:result_uint8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
3533 VUZP/VUZPQ:5:result_uint16x4 [] = { fff0, fff1, fff2, fff3, }
3534 VUZP/VUZPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3535 VUZP/VUZPQ:7:result_uint64x1 [] = { 3333333333333333, }
3536 VUZP/VUZPQ:8:result_poly8x8 [] = { f0, f1, f2, f3, f4, f5, f6, f7, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 3158 VUZP/VUZPQ chunk 0 output:
3182 VUZP/VUZPQ chunk 1 output:
|
| D | expected_input4gcc.txt | 3374 VUZP/VUZPQ chunk 0 output:
3400 VUZP/VUZPQ chunk 1 output:
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-uzp.ll | 81 ; Undef shuffle indices should not prevent matching to VUZP:
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 159 VUZP, // unzip (deinterleave) enumerator
|
| D | ARMISelLowering.cpp | 909 case ARMISD::VUZP: return "ARMISD::VUZP"; in getTargetNodeName()
4291 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4383 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4393 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
|
| D | ARMInstrNEON.td | 139 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
1879 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
4824 // VUZP : Vector Unzip (Deinterleave)
|
| D | ARMISelDAGToDAG.cpp | 2663 case ARMISD::VUZP: { in Select()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vuzp.ll | 67 ; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
201 ; Undef shuffle indices should not prevent matching to VUZP:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 157 VUZP, // unzip (deinterleave) enumerator
|
| D | ARMScheduleSwift.td | 584 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
|
| D | ARMISelLowering.cpp | 1212 case ARMISD::VUZP: return "ARMISD::VUZP"; in getTargetNodeName()
4711 return DAG.getNode(ARMISD::VUZP, DL, VT8Bit, N3, N3); in getCTPOP16BitCounts()
4769 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1); in lowerCTPOP32BitElements()
5595 return ARMISD::VUZP; in isNEONTwoResultShuffleMask()
5603 return ARMISD::VUZP; in isNEONTwoResultShuffleMask()
6164 return DAG.getNode(ARMISD::VUZP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
|
| D | ARMISelDAGToDAG.cpp | 3084 case ARMISD::VUZP: { in Select()
|
| D | ARMInstrNEON.td | 582 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
2532 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
6414 // VUZP : Vector Unzip (Deinterleave)
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 815 def VUZP : WInst<"vuzp", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 2112 ---- VUZP ----
|
| D | neon64.stdout.exp | 3367 ---- VUZP ----
|