| /external/libhevc/decoder/arm/ |
| D | ihevcd_fmt_conv_420sp_to_rgba8888.s | 232 VZIP.8 D14,D15
233 VZIP.8 D16,D17
234 VZIP.16 Q7,Q8
242 VZIP.8 D20,D21
243 VZIP.8 D22,D23
244 VZIP.16 Q10,Q11
246 VZIP.32 Q7,Q10
247 VZIP.32 Q8,Q11
283 VZIP.8 D14,D15
284 VZIP.8 D16,D17
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_sao_edge_offset_class1_chroma.s | 194 VZIP.8 D12,D13
213 VZIP.8 D24,D25
261 VZIP.8 D24,D25
344 VZIP.8 D12,D13
362 VZIP.8 D24,D25
397 VZIP.8 D24,D25
|
| D | ihevc_sao_band_offset_chroma.s | 371 VZIP.8 D5,D6
377 VZIP.8 D13,D14
386 VZIP.8 D17,D18
390 VZIP.8 D21,D22
|
| D | ihevc_sao_edge_offset_class0_chroma.s | 232 VZIP.S8 D16,D17
253 VZIP.S8 D26,D27 @II
397 VZIP.S8 D16,D17
420 VZIP.S8 D26,D27 @II
|
| D | ihevc_sao_edge_offset_class3_chroma.s | 423 VZIP.8 D22,D23 @I
544 VZIP.8 D24,D25 @II
569 VZIP.8 D22,D23 @III
657 VZIP.8 D22,D23
831 VZIP.8 D24,D25
1005 VZIP.8 D24,D25
|
| D | ihevc_sao_edge_offset_class2_chroma.s | 434 VZIP.8 D22,D23 @I
544 VZIP.8 D24,D25 @II
576 VZIP.8 D22,D23 @III
655 VZIP.8 D24,D25
807 VZIP.8 D24,D25
955 VZIP.8 D24,D25
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vzip.ll | 27 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
77 ; Undef shuffle indices should not prevent matching to VZIP:
|
| /external/arm-neon-tests/ |
| D | ref-rvct-neon.txt | 3579 VZIP/VZIPQ chunk 0 output:
3580 VZIP/VZIPQ:0:result_int8x8 [] = { fffffff0, fffffff4, 11, 11, fffffff1, fffffff5, 11, 11, }
3581 VZIP/VZIPQ:1:result_int16x4 [] = { fffffff0, fffffff2, 22, 22, }
3582 VZIP/VZIPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3583 VZIP/VZIPQ:3:result_int64x1 [] = { 3333333333333333, }
3584 VZIP/VZIPQ:4:result_uint8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
3585 VZIP/VZIPQ:5:result_uint16x4 [] = { fff0, fff2, 66, 66, }
3586 VZIP/VZIPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3587 VZIP/VZIPQ:7:result_uint64x1 [] = { 3333333333333333, }
3588 VZIP/VZIPQ:8:result_poly8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
[all …]
|
| D | ref-rvct-neon-nofp16.txt | 3359 VZIP/VZIPQ chunk 0 output:
3360 VZIP/VZIPQ:0:result_int8x8 [] = { fffffff0, fffffff4, 11, 11, fffffff1, fffffff5, 11, 11, }
3361 VZIP/VZIPQ:1:result_int16x4 [] = { fffffff0, fffffff2, 22, 22, }
3362 VZIP/VZIPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3363 VZIP/VZIPQ:3:result_int64x1 [] = { 3333333333333333, }
3364 VZIP/VZIPQ:4:result_uint8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
3365 VZIP/VZIPQ:5:result_uint16x4 [] = { fff0, fff2, 66, 66, }
3366 VZIP/VZIPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3367 VZIP/VZIPQ:7:result_uint64x1 [] = { 3333333333333333, }
3368 VZIP/VZIPQ:8:result_poly8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
[all …]
|
| D | ref-rvct-all.txt | 3579 VZIP/VZIPQ chunk 0 output:
3580 VZIP/VZIPQ:0:result_int8x8 [] = { fffffff0, fffffff4, 11, 11, fffffff1, fffffff5, 11, 11, }
3581 VZIP/VZIPQ:1:result_int16x4 [] = { fffffff0, fffffff2, 22, 22, }
3582 VZIP/VZIPQ:2:result_int32x2 [] = { fffffff0, fffffff1, }
3583 VZIP/VZIPQ:3:result_int64x1 [] = { 3333333333333333, }
3584 VZIP/VZIPQ:4:result_uint8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
3585 VZIP/VZIPQ:5:result_uint16x4 [] = { fff0, fff2, 66, 66, }
3586 VZIP/VZIPQ:6:result_uint32x2 [] = { fffffff0, fffffff1, }
3587 VZIP/VZIPQ:7:result_uint64x1 [] = { 3333333333333333, }
3588 VZIP/VZIPQ:8:result_poly8x8 [] = { f0, f4, 55, 55, f1, f5, 55, 55, }
[all …]
|
| D | expected_input4gcc-nofp16.txt | 3206 VZIP/VZIPQ chunk 0 output:
3230 VZIP/VZIPQ chunk 1 output:
|
| D | expected_input4gcc.txt | 3426 VZIP/VZIPQ chunk 0 output:
3452 VZIP/VZIPQ chunk 1 output:
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-zip.ll | 81 ; Undef shuffle indices should not prevent matching to VZIP:
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMISelLowering.h | 158 VZIP, // zip (interleave) enumerator
|
| D | ARMISelLowering.cpp | 908 case ARMISD::VZIP: return "ARMISD::VZIP"; in getTargetNodeName()
4295 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
4386 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
4396 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in LowerVECTOR_SHUFFLE()
|
| D | ARMInstrNEON.td | 138 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
1879 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
4834 // VZIP : Vector Zip (Interleave)
|
| D | ARMISelDAGToDAG.cpp | 2644 case ARMISD::VZIP: { in Select()
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vzip.ll | 67 ; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
201 ; Undef shuffle indices should not prevent matching to VZIP:
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 156 VZIP, // zip (interleave) enumerator
|
| D | ARMScheduleSwift.td | 584 (instregex "VSWP", "VTRN", "VUZP", "VZIP")>;
|
| D | ARMISelLowering.cpp | 1211 case ARMISD::VZIP: return "ARMISD::VZIP"; in getTargetNodeName()
5597 return ARMISD::VZIP; in isNEONTwoResultShuffleMask()
5605 return ARMISD::VZIP; in isNEONTwoResultShuffleMask()
6168 return DAG.getNode(ARMISD::VZIP, dl, DAG.getVTList(VT, VT), in GeneratePerfectShuffle()
|
| D | ARMISelDAGToDAG.cpp | 3063 case ARMISD::VZIP: { in Select()
|
| D | ARMInstrNEON.td | 581 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
2532 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
6426 // VZIP : Vector Zip (Interleave)
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 814 def VZIP : WInst<"vzip", "2dd", "csiUcUsUifPcPsQcQsQiQUcQUsQUiQfQPcQPs">;
|
| /external/valgrind/none/tests/arm/ |
| D | neon128.stdout.exp | 2093 ---- VZIP ----
|