Searched refs:VectorList (Results 1 – 4 of 4) sorted by relevance
| /external/eigen/Eigen/src/IterativeLinearSolvers/ |
| D | IncompleteCholesky.h | 65 typedef std::vector<std::list<StorageIndex> > VectorList; typedef
187 …, Ref<VectorSx> vals, const Index& col, const Index& jk, VectorIx& firstElt, VectorList& listCol);
222 VectorList listCol(n); // listCol(j) is a linked list of columns to update column j in factorize()
379 …dx, Ref<VectorSx> vals, const Index& col, const Index& jk, VectorIx& firstElt, VectorList& listCol) in updateList()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 573 struct VectorListOp VectorList; member
1420 return Kind == k_VectorList && !VectorList.isDoubleSpaced; in isSingleSpacedVectorList()
1423 return Kind == k_VectorList && VectorList.isDoubleSpaced; in isDoubleSpacedVectorList()
1427 return VectorList.Count == 1; in isVecListOneD()
1433 .contains(VectorList.RegNum)); in isVecListDPair()
1438 return VectorList.Count == 3; in isVecListThreeD()
1443 return VectorList.Count == 4; in isVecListFourD()
1450 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1455 return VectorList.Count == 3; in isVecListThreeQ()
1460 return VectorList.Count == 4; in isVecListFourQ()
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 253 struct VectorListOp VectorList; member
301 VectorList = o.VectorList; in AArch64Operand()
381 return VectorList.RegNum; in getVectorListStart()
386 return VectorList.Count; in getVectorListCount()
936 return Kind == k_VectorList && VectorList.Count == NumRegs && in isImplicitlyTypedVectorList()
937 !VectorList.ElementKind; in isImplicitlyTypedVectorList()
944 if (VectorList.Count != NumRegs) in isTypedVectorList()
946 if (VectorList.ElementKind != ElementKind) in isTypedVectorList()
948 return VectorList.NumElements == NumElements; in isTypedVectorList()
1639 Op->VectorList.RegNum = RegNum; in CreateVectorList()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64RegisterInfo.td | 487 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
588 defm VecListOne : VectorList<1, FPR64, FPR128>;
589 defm VecListTwo : VectorList<2, DD, QQ>;
590 defm VecListThree : VectorList<3, DDD, QQQ>;
591 defm VecListFour : VectorList<4, DDDD, QQQQ>;
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