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Searched refs:andi (Results 1 – 25 of 200) sorted by relevance

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/external/swiftshader/third_party/subzero/tests_lit/llvm2ice_tests/
Dvector-select.ll51 ; MIPS32: andi [[T3]],[[T3]],0xff
52 ; MIPS32: andi [[T3]],[[T3]],0x1
54 ; MIPS32: andi [[T2]],[[T2]],0xff
56 ; MIPS32: andi [[T1]],[[T1]],0xff
58 ; MIPS32: andi [[T1]],[[T1]],0xff
64 ; MIPS32: andi [[T14]],[[T14]],0xff
65 ; MIPS32: andi [[T14]],[[T14]],0x1
68 ; MIPS32: andi [[T3]],[[T3]],0xff
71 ; MIPS32: andi [[T2]],[[T2]],0xff
73 ; MIPS32: andi [[T2]],[[T2]],0xff
[all …]
Dvector-cast.ll37 ; MIPS32: andi t2,t2,0xff
38 ; MIPS32: andi t2,t2,0x1
41 ; MIPS32: andi t2,t2,0xff
47 ; MIPS32: andi v0,v0,0xff
48 ; MIPS32: andi v0,v0,0x1
51 ; MIPS32: andi v0,v0,0xff
59 ; MIPS32: andi t2,t2,0xff
60 ; MIPS32: andi t2,t2,0x1
63 ; MIPS32: andi t2,t2,0xff
70 ; MIPS32: andi a0,a0,0x1
[all …]
Dvector-icmp.ll38 ; MIPS32: andi [[T4]],[[T4]],0x1
41 ; MIPS32: andi [[T5]],[[T5]],0x1
44 ; MIPS32: andi [[T6]],[[T6]],0x1
47 ; MIPS32: andi [[T7]],[[T7]],0x1
285 ; MIPS32: andi [[T4:.*]],a0,0x1
286 ; MIPS32: andi [[T0]],[[T0]],0x1
291 ; MIPS32: andi [[T5:.*]],a1,0x1
292 ; MIPS32: andi [[T1]],[[T1]],0x1
297 ; MIPS32: andi [[T6:.*]],a2,0x1
298 ; MIPS32: andi [[T2]],[[T2]],0x1
[all …]
D8bit.pnacl.ll37 ; MIPS32: andi {{.*}},0xff
53 ; MIPS32: andi {{.*}},0xff
70 ; MIPS32: andi {{.*}},0xff
86 ; MIPS32: andi {{.*}},0xff
103 ; MIPS32: andi {{.*}},0xff
122 ; MIPS32: andi {{.*}},0xff
141 ; MIPS32: andi {{.*}},0xff
159 ; MIPS32: andi {{.*}},0xff
180 ; MIPS32: andi {{.*}},0xff
199 ; MIPS32: andi {{.*}},0xff
[all …]
Dvector-mips.ll64 ; MIPS32: andi a0,a0,0xff
88 ; MIPS32: andi a0,a0,0xffff
112 ; MIPS32: andi a0,a0,0x1
124 ; MIPS32: andi a2,a2,0x1
136 ; MIPS32: andi a0,a0,0xffff
137 ; MIPS32: andi a0,a0,0x1
150 ; MIPS32: andi a3,a3,0x1
162 ; MIPS32: andi a0,a0,0xff
163 ; MIPS32: andi a0,a0,0x1
176 ; MIPS32: andi a3,a3,0x1
Dvector-ops.ll152 ; MIPS32: andi [[ELT]],[[ELT]],0xff
238 ; MIPS32: andi [[ELT]],[[ELT]],0xff
293 ; MIPS32: andi a0,a0,0xffff
312 ; MIPS32: andi a0,a0,0xff
313 ; MIPS32: andi a0,a0,0xff
329 ; MIPS32: andi a1,a1,0x1
330 ; MIPS32: andi a1,a1,0x1
347 ; MIPS32: andi a0,a0,0x1
348 ; MIPS32: andi a0,a0,0x1
367 ; MIPS32: andi a0,a0,0xff
[all …]
Dsdiv.ll27 ; MIPS32: andi {{.*}},0xff
44 ; MIPS32: andi {{.*}},0xffff
74 ; MIPS32: andi {{.*}},0xff
91 ; MIPS32: andi {{.*}},0xffff
/external/llvm/test/CodeGen/Mips/llvm-ir/
Dand.ll168 ; GP32: andi $2, $4, 4
170 ; GP64: andi $2, $4, 4
182 ; GP32: andi $2, $4, 4
184 ; GP64: andi $2, $4, 4
196 ; GP32: andi $2, $4, 4
198 ; GP64: andi $2, $4, 4
210 ; GP32: andi $3, $5, 4
213 ; GP64: andi $2, $4, 4
218 ; MM64: andi $2, $4, 4
228 ; GP32: andi $5, $7, 4
[all …]
Durem.ll40 ; NOT-R6: andi $[[T0:[0-9]+]], $5, 1
41 ; NOT-R6: andi $[[T1:[0-9]+]], $4, 1
48 ; R6: andi $[[T0:[0-9]+]], $5, 1
49 ; R6: andi $[[T1:[0-9]+]], $4, 1
78 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
79 ; NOT-R2-R6: andi $[[T1:[0-9]+]], $4, 255
86 ; R2-R5: andi $[[T0:[0-9]+]], $5, 255
87 ; R2-R5: andi $[[T1:[0-9]+]], $4, 255
93 ; R6: andi $[[T0:[0-9]+]], $5, 255
94 ; R6: andi $[[T1:[0-9]+]], $4, 255
[all …]
Dselect-int.ll37 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
45 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
49 ; SEL: andi $[[T0:[0-9]+]], $4, 1
72 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
80 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
84 ; SEL: andi $[[T0:[0-9]+]], $4, 1
107 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
115 ; CMOV: andi $[[T0:[0-9]+]], $4, 1
119 ; SEL: andi $[[T0:[0-9]+]], $4, 1
142 ; M2: andi $[[T0:[0-9]+]], $4, 1
[all …]
Dashr.ll46 ; FIXME: The andi instruction is redundant.
47 ; GP32: andi $[[T0:[0-9]+]], $5, 255
48 ; GP64: andi $[[T0:[0-9]+]], $5, 255
60 ; FIXME: The andi instruction is redundant.
61 ; GP32: andi $[[T0:[0-9]+]], $5, 65535
62 ; GP64: andi $[[T0:[0-9]+]], $5, 65535
85 ; M2: andi $[[T1:[0-9]+]], $7, 32
107 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
114 ; 32R6: andi $[[T1:[0-9]+]], $7, 32
169 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
[all …]
Dlshr.ll47 ; GP32: andi $2, $[[T0]], 255
48 ; GP64: andi $2, $[[T0]], 255
60 ; GP32: andi $2, $[[T0]], 65535
61 ; GP64: andi $2, $[[T0]], 65535
83 ; M2: andi $[[T1:[0-9]+]], $7, 32
105 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
115 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
160 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
183 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
194 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
Dshl.ll46 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 255
51 ; R2-R6: andi $[[T0:[0-9]+]], $5, 255
67 ; NOT-R2-R6: andi $[[T0:[0-9]+]], $5, 65535
72 ; R2-R6: andi $[[T0:[0-9]+]], $5, 65535
99 ; M2: andi $[[T1:[0-9]+]], $7, 32
121 ; 32R1-R5: andi $[[T5:[0-9]+]], $7, 32
131 ; 32R6: andi $[[T5:[0-9]+]], $7, 32
176 ; M3: andi $[[T2:[0-9]+]], $[[T0]], 64
199 ; GP64-NOT-R6: andi $[[T5:[0-9]+]], $[[T2]], 64
210 ; 64R6: andi $[[T6:[0-9]+]], $[[T2]], 64
/external/valgrind/none/tests/mips64/
Dlogical_instructions.stdout.exp513 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
514 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff
515 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x0, imm 0x0000
516 andi $s0, $s1, 0x23 :: rt 0x0, rs 0x0, imm 0x0023
517 andi $t0, $t1, 0xff :: rt 0xaa, rs 0x12bd6aa, imm 0x00ff
518 andi $t2, $t3, 0xffff :: rt 0xd6aa, rs 0x12bd6aa, imm 0xffff
519 andi $a0, $a1, 0x0 :: rt 0x0, rs 0x12bd6aa, imm 0x0000
520 andi $s0, $s1, 0x23 :: rt 0x22, rs 0x12bd6aa, imm 0x0023
521 andi $t0, $t1, 0xff :: rt 0x0, rs 0x0, imm 0x00ff
522 andi $t2, $t3, 0xffff :: rt 0x0, rs 0x0, imm 0xffff
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/MBlaze/
Dshift.ll13 ; FUN: andi
30 ; FUN: andi
33 ; SHT-NOT: andi
49 ; FUN: andi
66 ; FUN: andi
69 ; SHT-NOT: andi
85 ; FUN: andi
88 ; SHT-NOT: andi
103 ; FUN: andi
106 ; SHT-NOT: andi
/external/llvm/test/CodeGen/PowerPC/
Dcrbit-asm.ll14 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
17 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
33 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
36 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
49 ; CHECK-DAG: andi. {{[0-9]+}}, 3, 1
52 ; CHECK-DAG: andi. {{[0-9]+}}, 4, 1
/external/llvm/test/CodeGen/Mips/
Dfcmp.ll52 ; 32-CMP-DAG: andi $2, $[[T1]], 1
56 ; 64-CMP-DAG: andi $2, $[[T1]], 1
86 ; 32-CMP-DAG: andi $2, $[[T1]], 1
90 ; 64-CMP-DAG: andi $2, $[[T1]], 1
120 ; 32-CMP-DAG: andi $2, $[[T1]], 1
124 ; 64-CMP-DAG: andi $2, $[[T1]], 1
154 ; 32-CMP-DAG: andi $2, $[[T1]], 1
158 ; 64-CMP-DAG: andi $2, $[[T1]], 1
188 ; 32-CMP-DAG: andi $2, $[[T1]], 1
192 ; 64-CMP-DAG: andi $2, $[[T1]], 1
[all …]
/external/swiftshader/third_party/subzero/tests_lit/assembler/mips32/
Dencoding_test_fcmp.ll35 ; ASM-NEXT: andi $v0, $v0, 1
40 ; DIS-NEXT: 4: 30420001 andi v0,v0,0x1
68 ; ASM-NEXT: andi $v0, $v0, 1
73 ; DIS-NEXT: 14: 30420001 andi v0,v0,0x1
103 ; ASM-NEXT: andi $v0, $v0, 1
110 ; DIS-NEXT: 2c: 30420001 andi v0,v0,0x1
148 ; ASM-NEXT: andi $v0, $v0, 1
155 ; DIS-NEXT: 4c: 30420001 andi v0,v0,0x1
193 ; ASM-NEXT: andi $v0, $v0, 1
200 ; DIS-NEXT: 6c: 30420001 andi v0,v0,0x1
[all …]
/external/llvm/test/MC/Mips/
Dmicromips-alu-instructions.s27 # CHECK-EL: andi $9, $6, 17767 # encoding: [0x26,0xd1,0x67,0x45]
28 # CHECK-EL: andi $9, $6, 17767 # encoding: [0x26,0xd1,0x67,0x45]
44 # CHECK-EL: andi $3, $3, 5 # encoding: [0x63,0xd0,0x05,0x00]
70 # CHECK-EB: andi $9, $6, 17767 # encoding: [0xd1,0x26,0x45,0x67]
71 # CHECK-EB: andi $9, $6, 17767 # encoding: [0xd1,0x26,0x45,0x67]
87 # CHECK-EB: andi $3, $3, 5 # encoding: [0xd0,0x63,0x00,0x05]
112 andi $9, $6, 17767
Dmips-alu-instructions.s8 # CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
9 # CHECK: andi $9, $6, 17767 # encoding: [0x67,0x45,0xc9,0x30]
10 # CHECK: andi $9, $9, 17767 # encoding: [0x67,0x45,0x29,0x31]
40 andi $9, $6, 17767
41 andi $9, 17767
/external/llvm/test/MC/PowerPC/
Dppc64-operands.s151 # CHECK-BE: andi. 0, 3, 32767 # encoding: [0x70,0x60,0x7f,0xff]
152 # CHECK-LE: andi. 0, 3, 32767 # encoding: [0xff,0x7f,0x60,0x70]
153 andi. %r0,%r3,~0x8000@l
155 # CHECK-BE: andi. 0, 3, 0 # encoding: [0x70,0x60,0x00,0x00]
156 # CHECK-LE: andi. 0, 3, 0 # encoding: [0x00,0x00,0x60,0x70]
157 andi. %r0,%r3,!0x8000@l
/external/llvm/test/CodeGen/Mips/Fast-ISel/
Dsel1.ll11 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
28 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
45 ; CHECK-NEXT: andi $[[T4:[0-9]+]], $[[T3]], 1
60 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
76 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
92 ; CHECK-NEXT: andi $[[T2:[0-9]+]], $[[T1]], 1
Dicmpa.ll28 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
49 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
69 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
89 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
109 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
129 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
148 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
167 ; CHECK: andi ${{[0-9]+}}, $[[REG1]], 1
188 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
207 ; CHECK: andi ${{[0-9]+}}, $[[REG2]], 1
Dbswap1.ll25 ; 32R1: andi $[[TMP4:[0-9]+]], $[[TMP3]], 65535
43 ; 32R1: andi $[[TMP3:[0-9]+]], $[[TMP1]], 65280
45 ; 32R1: andi $[[TMP5:[0-9]+]], $[[B_VAL]], 65280
/external/v8/src/ppc/
Dcodegen-ppc.cc89 __ andi(r0, result, Operand(kIsIndirectStringMask)); in Generate() local
94 __ andi(ip, result, Operand(kStringRepresentationMask)); in Generate() local
131 __ andi(r0, result, Operand(kStringRepresentationMask)); in Generate() local
145 __ andi(r0, result, Operand(kIsIndirectStringMask)); in Generate() local
150 __ andi(r0, result, Operand(kShortExternalStringMask)); in Generate() local
158 __ andi(r0, result, Operand(kStringEncodingMask)); in Generate() local

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