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1; RUN: llc < %s -march=mips -mcpu=mips32 | \
2; RUN:    FileCheck %s -check-prefixes=ALL,32-C
3; RUN: llc < %s -march=mips -mcpu=mips32r2 | \
4; RUN:    FileCheck %s -check-prefixes=ALL,32-C
5; RUN: llc < %s -march=mips -mcpu=mips32r6 | \
6; RUN:    FileCheck %s -check-prefixes=ALL,32-CMP
7; RUN: llc < %s -march=mips64 -mcpu=mips4 | \
8; RUN:    FileCheck %s -check-prefixes=ALL,64-C
9; RUN: llc < %s -march=mips64 -mcpu=mips64 | \
10; RUN:    FileCheck %s -check-prefixes=ALL,64-C
11; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | \
12; RUN:    FileCheck %s -check-prefixes=ALL,64-C
13; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | \
14; RUN:    FileCheck %s -check-prefixes=ALL,64-CMP
15; RUN: llc < %s -march=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
16; RUN:    -check-prefixes=ALL,MM,MM32R3
17; RUN: llc < %s -march=mips -mcpu=mips32r6 -mattr=+micromips | FileCheck %s \
18; RUN:    -check-prefixes=ALL,MM,MMR6,MM32R6
19; RUN: llc < %s -march=mips64 -mcpu=mips64r6 -mattr=+micromips | FileCheck %s \
20; RUN:    -check-prefixes=ALL,MM,MMR6,MM64R6
21
22define i32 @false_f32(float %a, float %b) nounwind {
23; ALL-LABEL: false_f32:
24; 32-C:          addiu $2, $zero, 0
25
26; 32-CMP:        addiu $2, $zero, 0
27
28; 64-C:          addiu $2, $zero, 0
29
30; 64-CMP:        addiu $2, $zero, 0
31
32; MM-DAG:        lui $2, 0
33
34  %1 = fcmp false float %a, %b
35  %2 = zext i1 %1 to i32
36  ret i32 %2
37}
38
39define i32 @oeq_f32(float %a, float %b) nounwind {
40; ALL-LABEL: oeq_f32:
41
42; 32-C-DAG:      addiu $2, $zero, 1
43; 32-C-DAG:      c.eq.s $f12, $f14
44; 32-C:          movf $2, $zero, $fcc0
45
46; 64-C-DAG:      addiu $2, $zero, 1
47; 64-C-DAG:      c.eq.s $f12, $f13
48; 64-C:          movf $2, $zero, $fcc0
49
50; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
51; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
52; 32-CMP-DAG:    andi $2, $[[T1]], 1
53
54; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
55; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
56; 64-CMP-DAG:    andi $2, $[[T1]], 1
57
58; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
59; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
60; MM32R3-DAG:    c.eq.s $f12, $f14
61; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
62
63; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
64; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
65; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
66; MMR6-DAG:      andi16 $2, $[[T1]], 1
67
68  %1 = fcmp oeq float %a, %b
69  %2 = zext i1 %1 to i32
70  ret i32 %2
71}
72
73define i32 @ogt_f32(float %a, float %b) nounwind {
74; ALL-LABEL: ogt_f32:
75
76; 32-C-DAG:      addiu $2, $zero, 1
77; 32-C-DAG:      c.ule.s $f12, $f14
78; 32-C:          movt $2, $zero, $fcc0
79
80; 64-C-DAG:      addiu $2, $zero, 1
81; 64-C-DAG:      c.ule.s $f12, $f13
82; 64-C:          movt $2, $zero, $fcc0
83
84; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
85; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
86; 32-CMP-DAG:    andi $2, $[[T1]], 1
87
88; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
89; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
90; 64-CMP-DAG:    andi $2, $[[T1]], 1
91
92; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
93; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
94; MM32R3-DAG:    c.ule.s $f12, $f14
95; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
96
97; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f14, $f12
98; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f13, $f12
99; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
100; MMR6-DAG:      andi16 $2, $[[T1]], 1
101
102  %1 = fcmp ogt float %a, %b
103  %2 = zext i1 %1 to i32
104  ret i32 %2
105}
106
107define i32 @oge_f32(float %a, float %b) nounwind {
108; ALL-LABEL: oge_f32:
109
110; 32-C-DAG:      addiu $2, $zero, 1
111; 32-C-DAG:      c.ult.s $f12, $f14
112; 32-C:          movt $2, $zero, $fcc0
113
114; 64-C-DAG:      addiu $2, $zero, 1
115; 64-C-DAG:      c.ult.s $f12, $f13
116; 64-C:          movt $2, $zero, $fcc0
117
118; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
119; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
120; 32-CMP-DAG:    andi $2, $[[T1]], 1
121
122; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
123; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
124; 64-CMP-DAG:    andi $2, $[[T1]], 1
125
126; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
127; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
128; MM32R3-DAG:    c.ult.s $f12, $f14
129; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
130
131; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f14, $f12
132; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f13, $f12
133; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
134; MMR6-DAG:      andi16 $2, $[[T1]], 1
135
136  %1 = fcmp oge float %a, %b
137  %2 = zext i1 %1 to i32
138  ret i32 %2
139}
140
141define i32 @olt_f32(float %a, float %b) nounwind {
142; ALL-LABEL: olt_f32:
143
144; 32-C-DAG:      addiu $2, $zero, 1
145; 32-C-DAG:      c.olt.s $f12, $f14
146; 32-C:          movf $2, $zero, $fcc0
147
148; 64-C-DAG:      addiu $2, $zero, 1
149; 64-C-DAG:      c.olt.s $f12, $f13
150; 64-C:          movf $2, $zero, $fcc0
151
152; 32-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
153; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
154; 32-CMP-DAG:    andi $2, $[[T1]], 1
155
156; 64-CMP-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
157; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
158; 64-CMP-DAG:    andi $2, $[[T1]], 1
159
160; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
161; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
162; MM32R3-DAG:    c.olt.s $f12, $f14
163; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
164
165; MM32R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f14
166; MM64R6-DAG:    cmp.lt.s $[[T0:f[0-9]+]], $f12, $f13
167; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
168; MMR6-DAG:      andi16 $2, $[[T1]], 1
169
170  %1 = fcmp olt float %a, %b
171  %2 = zext i1 %1 to i32
172  ret i32 %2
173}
174
175define i32 @ole_f32(float %a, float %b) nounwind {
176; ALL-LABEL: ole_f32:
177
178; 32-C-DAG:      addiu $2, $zero, 1
179; 32-C-DAG:      c.ole.s $f12, $f14
180; 32-C:          movf $2, $zero, $fcc0
181
182; 64-C-DAG:      addiu $2, $zero, 1
183; 64-C-DAG:      c.ole.s $f12, $f13
184; 64-C:          movf $2, $zero, $fcc0
185
186; 32-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
187; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
188; 32-CMP-DAG:    andi $2, $[[T1]], 1
189
190; 64-CMP-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
191; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
192; 64-CMP-DAG:    andi $2, $[[T1]], 1
193
194; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
195; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
196; MM32R3-DAG:    c.ole.s $f12, $f14
197; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
198
199; MM32R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f14
200; MM64R6-DAG:    cmp.le.s $[[T0:f[0-9]+]], $f12, $f13
201; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
202; MMR6-DAG:      andi16 $2, $[[T1]], 1
203
204  %1 = fcmp ole float %a, %b
205  %2 = zext i1 %1 to i32
206  ret i32 %2
207}
208
209define i32 @one_f32(float %a, float %b) nounwind {
210; ALL-LABEL: one_f32:
211
212; 32-C-DAG:      addiu $2, $zero, 1
213; 32-C-DAG:      c.ueq.s $f12, $f14
214; 32-C:          movt $2, $zero, $fcc0
215
216; 64-C-DAG:      addiu $2, $zero, 1
217; 64-C-DAG:      c.ueq.s $f12, $f13
218; 64-C:          movt $2, $zero, $fcc0
219
220; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
221; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
222; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
223; 32-CMP-DAG:    andi $2, $[[T2]], 1
224
225; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
226; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
227; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
228; 64-CMP-DAG:    andi $2, $[[T2]], 1
229
230; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
231; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
232; MM32R3-DAG:    c.ueq.s $f12, $f14
233; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
234
235; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
236; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
237; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
238; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
239; MMR6-DAG:      andi16 $2, $[[T2]], 1
240
241  %1 = fcmp one float %a, %b
242  %2 = zext i1 %1 to i32
243  ret i32 %2
244}
245
246define i32 @ord_f32(float %a, float %b) nounwind {
247; ALL-LABEL: ord_f32:
248
249; 32-C-DAG:      addiu $2, $zero, 1
250; 32-C-DAG:      c.un.s $f12, $f14
251; 32-C:          movt $2, $zero, $fcc0
252
253; 64-C-DAG:      addiu $2, $zero, 1
254; 64-C-DAG:      c.un.s $f12, $f13
255; 64-C:          movt $2, $zero, $fcc0
256
257; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
258; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
259; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
260; 32-CMP-DAG:    andi $2, $[[T2]], 1
261
262; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
263; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
264; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
265; 64-CMP-DAG:    andi $2, $[[T2]], 1
266
267; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
268; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
269; MM32R3-DAG:    c.un.s  $f12, $f14
270; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
271
272; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
273; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
274; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
275; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
276; MMR6-DAG:      andi16 $2, $[[T2]], 1
277
278  %1 = fcmp ord float %a, %b
279  %2 = zext i1 %1 to i32
280  ret i32 %2
281}
282
283define i32 @ueq_f32(float %a, float %b) nounwind {
284; ALL-LABEL: ueq_f32:
285
286; 32-C-DAG:      addiu $2, $zero, 1
287; 32-C-DAG:      c.ueq.s $f12, $f14
288; 32-C:          movf $2, $zero, $fcc0
289
290; 64-C-DAG:      addiu $2, $zero, 1
291; 64-C-DAG:      c.ueq.s $f12, $f13
292; 64-C:          movf $2, $zero, $fcc0
293
294; 32-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
295; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
296; 32-CMP-DAG:    andi $2, $[[T1]], 1
297
298; 64-CMP-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
299; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
300; 64-CMP-DAG:    andi $2, $[[T1]], 1
301
302; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
303; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
304; MM32R3-DAG:    c.ueq.s $f12, $f14
305; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
306
307; MM32R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f14
308; MM64R6-DAG:    cmp.ueq.s $[[T0:f[0-9]+]], $f12, $f13
309; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
310; MMR6-DAG:      andi16 $2, $[[T1]], 1
311
312  %1 = fcmp ueq float %a, %b
313  %2 = zext i1 %1 to i32
314  ret i32 %2
315}
316
317define i32 @ugt_f32(float %a, float %b) nounwind {
318; ALL-LABEL: ugt_f32:
319
320; 32-C-DAG:      addiu $2, $zero, 1
321; 32-C-DAG:      c.ole.s $f12, $f14
322; 32-C:          movt $2, $zero, $fcc0
323
324; 64-C-DAG:      addiu $2, $zero, 1
325; 64-C-DAG:      c.ole.s $f12, $f13
326; 64-C:          movt $2, $zero, $fcc0
327
328; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
329; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
330; 32-CMP-DAG:    andi $2, $[[T1]], 1
331
332; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
333; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
334; 64-CMP-DAG:    andi $2, $[[T1]], 1
335
336; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
337; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
338; MM32R3-DAG:    c.ole.s $f12, $f14
339; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
340
341; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f14, $f12
342; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f13, $f12
343; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
344; MMR6-DAG:      andi16 $2, $[[T1]], 1
345
346  %1 = fcmp ugt float %a, %b
347  %2 = zext i1 %1 to i32
348  ret i32 %2
349}
350
351define i32 @uge_f32(float %a, float %b) nounwind {
352; ALL-LABEL: uge_f32:
353
354; 32-C-DAG:      addiu $2, $zero, 1
355; 32-C-DAG:      c.olt.s $f12, $f14
356; 32-C:          movt $2, $zero, $fcc0
357
358; 64-C-DAG:      addiu $2, $zero, 1
359; 64-C-DAG:      c.olt.s $f12, $f13
360; 64-C:          movt $2, $zero, $fcc0
361
362; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
363; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
364; 32-CMP-DAG:    andi $2, $[[T1]], 1
365
366; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
367; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
368; 64-CMP-DAG:    andi $2, $[[T1]], 1
369
370; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
371; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
372; MM32R3-DAG:    c.olt.s $f12, $f14
373; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
374
375; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f14, $f12
376; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f13, $f12
377; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
378; MMR6-DAG:      andi16 $2, $[[T1]], 1
379
380  %1 = fcmp uge float %a, %b
381  %2 = zext i1 %1 to i32
382  ret i32 %2
383}
384
385define i32 @ult_f32(float %a, float %b) nounwind {
386; ALL-LABEL: ult_f32:
387
388; 32-C-DAG:      addiu $2, $zero, 1
389; 32-C-DAG:      c.ult.s $f12, $f14
390; 32-C:          movf $2, $zero, $fcc0
391
392; 64-C-DAG:      addiu $2, $zero, 1
393; 64-C-DAG:      c.ult.s $f12, $f13
394; 64-C:          movf $2, $zero, $fcc0
395
396; 32-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
397; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
398; 32-CMP-DAG:    andi $2, $[[T1]], 1
399
400; 64-CMP-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
401; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
402; 64-CMP-DAG:    andi $2, $[[T1]], 1
403
404; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
405; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
406; MM32R3-DAG:    c.ult.s $f12, $f14
407; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
408
409; MM32R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f14
410; MM64R6-DAG:    cmp.ult.s $[[T0:f[0-9]+]], $f12, $f13
411; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
412; MMR6-DAG:      andi16 $2, $[[T1]], 1
413
414  %1 = fcmp ult float %a, %b
415  %2 = zext i1 %1 to i32
416  ret i32 %2
417}
418
419define i32 @ule_f32(float %a, float %b) nounwind {
420; ALL-LABEL: ule_f32:
421
422; 32-C-DAG:      addiu $2, $zero, 1
423; 32-C-DAG:      c.ule.s $f12, $f14
424; 32-C:          movf $2, $zero, $fcc0
425
426; 64-C-DAG:      addiu $2, $zero, 1
427; 64-C-DAG:      c.ule.s $f12, $f13
428; 64-C:          movf $2, $zero, $fcc0
429
430; 32-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
431; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
432; 32-CMP-DAG:    andi $2, $[[T1]], 1
433
434; 64-CMP-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
435; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
436; 64-CMP-DAG:    andi $2, $[[T1]], 1
437
438; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
439; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
440; MM32R3-DAG:    c.ule.s $f12, $f14
441; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
442
443; MM32R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f14
444; MM64R6-DAG:    cmp.ule.s $[[T0:f[0-9]+]], $f12, $f13
445; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
446; MMR6-DAG:      andi16 $2, $[[T1]], 1
447
448  %1 = fcmp ule float %a, %b
449  %2 = zext i1 %1 to i32
450  ret i32 %2
451}
452
453define i32 @une_f32(float %a, float %b) nounwind {
454; ALL-LABEL: une_f32:
455
456; 32-C-DAG:      addiu $2, $zero, 1
457; 32-C-DAG:      c.eq.s $f12, $f14
458; 32-C:          movt $2, $zero, $fcc0
459
460; 64-C-DAG:      addiu $2, $zero, 1
461; 64-C-DAG:      c.eq.s $f12, $f13
462; 64-C:          movt $2, $zero, $fcc0
463
464; 32-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
465; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
466; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
467; 32-CMP-DAG:    andi $2, $[[T2]], 1
468
469; 64-CMP-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
470; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
471; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
472; 64-CMP-DAG:    andi $2, $[[T2]], 1
473
474; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
475; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
476; MM32R3-DAG:    c.eq.s $f12, $f14
477; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
478
479; MM32R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f14
480; MM64R6-DAG:    cmp.eq.s $[[T0:f[0-9]+]], $f12, $f13
481; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
482; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
483; MMR6-DAG:      andi16 $2, $[[T2]], 1
484
485  %1 = fcmp une float %a, %b
486  %2 = zext i1 %1 to i32
487  ret i32 %2
488}
489
490define i32 @uno_f32(float %a, float %b) nounwind {
491; ALL-LABEL: uno_f32:
492
493; 32-C-DAG:      addiu $2, $zero, 1
494; 32-C-DAG:      c.un.s $f12, $f14
495; 32-C:          movf $2, $zero, $fcc0
496
497; 64-C-DAG:      addiu $2, $zero, 1
498; 64-C-DAG:      c.un.s $f12, $f13
499; 64-C:          movf $2, $zero, $fcc0
500
501; 32-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
502; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
503; 32-CMP-DAG:    andi $2, $[[T1]], 1
504
505; 64-CMP-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
506; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
507; 64-CMP-DAG:    andi $2, $[[T1]], 1
508
509; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
510; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
511; MM32R3-DAG:    c.un.s $f12, $f14
512; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
513
514; MM32R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f14
515; MM64R6-DAG:    cmp.un.s $[[T0:f[0-9]+]], $f12, $f13
516; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
517; MMR6-DAG:      andi16 $2, $[[T1]], 1
518
519  %1 = fcmp uno float %a, %b
520  %2 = zext i1 %1 to i32
521  ret i32 %2
522}
523
524define i32 @true_f32(float %a, float %b) nounwind {
525; ALL-LABEL: true_f32:
526; 32-C:          addiu $2, $zero, 1
527
528; 32-CMP:        addiu $2, $zero, 1
529
530; 64-C:          addiu $2, $zero, 1
531
532; 64-CMP:        addiu $2, $zero, 1
533
534; MM-DAG:        li16 $2, 1
535
536  %1 = fcmp true float %a, %b
537  %2 = zext i1 %1 to i32
538  ret i32 %2
539}
540
541define i32 @false_f64(double %a, double %b) nounwind {
542; ALL-LABEL: false_f64:
543; 32-C:          addiu $2, $zero, 0
544
545; 32-CMP:        addiu $2, $zero, 0
546
547; 64-C:          addiu $2, $zero, 0
548
549; 64-CMP:        addiu $2, $zero, 0
550
551; MM-DAG:        lui $2, 0
552
553  %1 = fcmp false double %a, %b
554  %2 = zext i1 %1 to i32
555  ret i32 %2
556}
557
558define i32 @oeq_f64(double %a, double %b) nounwind {
559; ALL-LABEL: oeq_f64:
560
561; 32-C-DAG:      addiu $2, $zero, 1
562; 32-C-DAG:      c.eq.d $f12, $f14
563; 32-C:          movf $2, $zero, $fcc0
564
565; 64-C-DAG:      addiu $2, $zero, 1
566; 64-C-DAG:      c.eq.d $f12, $f13
567; 64-C:          movf $2, $zero, $fcc0
568
569; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
570; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
571; 32-CMP-DAG:    andi $2, $[[T1]], 1
572
573; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
574; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
575; 64-CMP-DAG:    andi $2, $[[T1]], 1
576
577; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
578; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
579; MM32R3-DAG:    c.eq.d $f12, $f14
580; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
581
582; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
583; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
584; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
585; MMR6-DAG:      andi16 $2, $[[T1]], 1
586
587  %1 = fcmp oeq double %a, %b
588  %2 = zext i1 %1 to i32
589  ret i32 %2
590}
591
592define i32 @ogt_f64(double %a, double %b) nounwind {
593; ALL-LABEL: ogt_f64:
594
595; 32-C-DAG:      addiu $2, $zero, 1
596; 32-C-DAG:      c.ule.d $f12, $f14
597; 32-C:          movt $2, $zero, $fcc0
598
599; 64-C-DAG:      addiu $2, $zero, 1
600; 64-C-DAG:      c.ule.d $f12, $f13
601; 64-C:          movt $2, $zero, $fcc0
602
603; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
604; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
605; 32-CMP-DAG:    andi $2, $[[T1]], 1
606
607; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
608; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
609; 64-CMP-DAG:    andi $2, $[[T1]], 1
610
611; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
612; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
613; MM32R3-DAG:    c.ule.d $f12, $f14
614; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
615
616; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f14, $f12
617; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f13, $f12
618; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
619; MMR6-DAG:      andi16 $2, $[[T1]], 1
620
621  %1 = fcmp ogt double %a, %b
622  %2 = zext i1 %1 to i32
623  ret i32 %2
624}
625
626define i32 @oge_f64(double %a, double %b) nounwind {
627; ALL-LABEL: oge_f64:
628
629; 32-C-DAG:      addiu $2, $zero, 1
630; 32-C-DAG:      c.ult.d $f12, $f14
631; 32-C:          movt $2, $zero, $fcc0
632
633; 64-C-DAG:      addiu $2, $zero, 1
634; 64-C-DAG:      c.ult.d $f12, $f13
635; 64-C:          movt $2, $zero, $fcc0
636
637; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
638; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
639; 32-CMP-DAG:    andi $2, $[[T1]], 1
640
641; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
642; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
643; 64-CMP-DAG:    andi $2, $[[T1]], 1
644
645; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
646; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
647; MM32R3-DAG:    c.ult.d $f12, $f14
648; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
649
650; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f14, $f12
651; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f13, $f12
652; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
653; MMR6-DAG:      andi16 $2, $[[T1]], 1
654
655  %1 = fcmp oge double %a, %b
656  %2 = zext i1 %1 to i32
657  ret i32 %2
658}
659
660define i32 @olt_f64(double %a, double %b) nounwind {
661; ALL-LABEL: olt_f64:
662
663; 32-C-DAG:      addiu $2, $zero, 1
664; 32-C-DAG:      c.olt.d $f12, $f14
665; 32-C:          movf $2, $zero, $fcc0
666
667; 64-C-DAG:      addiu $2, $zero, 1
668; 64-C-DAG:      c.olt.d $f12, $f13
669; 64-C:          movf $2, $zero, $fcc0
670
671; 32-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
672; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
673; 32-CMP-DAG:    andi $2, $[[T1]], 1
674
675; 64-CMP-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
676; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
677; 64-CMP-DAG:    andi $2, $[[T1]], 1
678
679; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
680; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
681; MM32R3-DAG:    c.olt.d $f12, $f14
682; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
683
684; MM32R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f14
685; MM64R6-DAG:    cmp.lt.d $[[T0:f[0-9]+]], $f12, $f13
686; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
687; MMR6-DAG:      andi16 $2, $[[T1]], 1
688
689  %1 = fcmp olt double %a, %b
690  %2 = zext i1 %1 to i32
691  ret i32 %2
692}
693
694define i32 @ole_f64(double %a, double %b) nounwind {
695; ALL-LABEL: ole_f64:
696
697; 32-C-DAG:      addiu $2, $zero, 1
698; 32-C-DAG:      c.ole.d $f12, $f14
699; 32-C:          movf $2, $zero, $fcc0
700
701; 64-C-DAG:      addiu $2, $zero, 1
702; 64-C-DAG:      c.ole.d $f12, $f13
703; 64-C:          movf $2, $zero, $fcc0
704
705; 32-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
706; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
707; 32-CMP-DAG:    andi $2, $[[T1]], 1
708
709; 64-CMP-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
710; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
711; 64-CMP-DAG:    andi $2, $[[T1]], 1
712
713; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
714; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
715; MM32R3-DAG:    c.ole.d $f12, $f14
716; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
717
718; MM32R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f14
719; MM64R6-DAG:    cmp.le.d $[[T0:f[0-9]+]], $f12, $f13
720; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
721; MMR6-DAG:      andi16 $2, $[[T1]], 1
722
723  %1 = fcmp ole double %a, %b
724  %2 = zext i1 %1 to i32
725  ret i32 %2
726}
727
728define i32 @one_f64(double %a, double %b) nounwind {
729; ALL-LABEL: one_f64:
730
731; 32-C-DAG:      addiu $2, $zero, 1
732; 32-C-DAG:      c.ueq.d $f12, $f14
733; 32-C:          movt $2, $zero, $fcc0
734
735; 64-C-DAG:      addiu $2, $zero, 1
736; 64-C-DAG:      c.ueq.d $f12, $f13
737; 64-C:          movt $2, $zero, $fcc0
738
739; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
740; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
741; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
742; 32-CMP-DAG:    andi $2, $[[T2]], 1
743
744; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
745; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
746; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
747; 64-CMP-DAG:    andi $2, $[[T2]], 1
748
749; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
750; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
751; MM32R3-DAG:    c.ueq.d $f12, $f14
752; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
753
754; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
755; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
756; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
757; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
758; MMR6-DAG:      andi16 $2, $[[T2]], 1
759
760  %1 = fcmp one double %a, %b
761  %2 = zext i1 %1 to i32
762  ret i32 %2
763}
764
765define i32 @ord_f64(double %a, double %b) nounwind {
766; ALL-LABEL: ord_f64:
767
768; 32-C-DAG:      addiu $2, $zero, 1
769; 32-C-DAG:      c.un.d $f12, $f14
770; 32-C:          movt $2, $zero, $fcc0
771
772; 64-C-DAG:      addiu $2, $zero, 1
773; 64-C-DAG:      c.un.d $f12, $f13
774; 64-C:          movt $2, $zero, $fcc0
775
776; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
777; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
778; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
779; 32-CMP-DAG:    andi $2, $[[T2]], 1
780
781; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
782; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
783; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
784; 64-CMP-DAG:    andi $2, $[[T2]], 1
785
786; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
787; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
788; MM32R3-DAG:    c.un.d $f12, $f14
789; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
790
791; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
792; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
793; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
794; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
795; MMR6-DAG:      andi16 $2, $[[T2]], 1
796
797  %1 = fcmp ord double %a, %b
798  %2 = zext i1 %1 to i32
799  ret i32 %2
800}
801
802define i32 @ueq_f64(double %a, double %b) nounwind {
803; ALL-LABEL: ueq_f64:
804
805; 32-C-DAG:      addiu $2, $zero, 1
806; 32-C-DAG:      c.ueq.d $f12, $f14
807; 32-C:          movf $2, $zero, $fcc0
808
809; 64-C-DAG:      addiu $2, $zero, 1
810; 64-C-DAG:      c.ueq.d $f12, $f13
811; 64-C:          movf $2, $zero, $fcc0
812
813; 32-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
814; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
815; 32-CMP-DAG:    andi $2, $[[T1]], 1
816
817; 64-CMP-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
818; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
819; 64-CMP-DAG:    andi $2, $[[T1]], 1
820
821; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
822; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
823; MM32R3-DAG:    c.ueq.d $f12, $f14
824; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
825
826; MM32R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f14
827; MM64R6-DAG:    cmp.ueq.d $[[T0:f[0-9]+]], $f12, $f13
828; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
829; MMR6-DAG:      andi16 $2, $[[T1]], 1
830
831  %1 = fcmp ueq double %a, %b
832  %2 = zext i1 %1 to i32
833  ret i32 %2
834}
835
836define i32 @ugt_f64(double %a, double %b) nounwind {
837; ALL-LABEL: ugt_f64:
838
839; 32-C-DAG:      addiu $2, $zero, 1
840; 32-C-DAG:      c.ole.d $f12, $f14
841; 32-C:          movt $2, $zero, $fcc0
842
843; 64-C-DAG:      addiu $2, $zero, 1
844; 64-C-DAG:      c.ole.d $f12, $f13
845; 64-C:          movt $2, $zero, $fcc0
846
847; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
848; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
849; 32-CMP-DAG:    andi $2, $[[T1]], 1
850
851; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
852; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
853; 64-CMP-DAG:    andi $2, $[[T1]], 1
854
855; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
856; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
857; MM32R3-DAG:    c.ole.d $f12, $f14
858; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
859
860; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f14, $f12
861; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f13, $f12
862; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
863; MMR6-DAG:      andi16 $2, $[[T1]], 1
864
865  %1 = fcmp ugt double %a, %b
866  %2 = zext i1 %1 to i32
867  ret i32 %2
868}
869
870define i32 @uge_f64(double %a, double %b) nounwind {
871; ALL-LABEL: uge_f64:
872
873; 32-C-DAG:      addiu $2, $zero, 1
874; 32-C-DAG:      c.olt.d $f12, $f14
875; 32-C:          movt $2, $zero, $fcc0
876
877; 64-C-DAG:      addiu $2, $zero, 1
878; 64-C-DAG:      c.olt.d $f12, $f13
879; 64-C:          movt $2, $zero, $fcc0
880
881; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
882; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
883; 32-CMP-DAG:    andi $2, $[[T1]], 1
884
885; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
886; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
887; 64-CMP-DAG:    andi $2, $[[T1]], 1
888
889; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
890; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
891; MM32R3-DAG:    c.olt.d $f12, $f14
892; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
893
894; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f14, $f12
895; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f13, $f12
896; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
897; MMR6-DAG:      andi16 $2, $[[T1]], 1
898
899  %1 = fcmp uge double %a, %b
900  %2 = zext i1 %1 to i32
901  ret i32 %2
902}
903
904define i32 @ult_f64(double %a, double %b) nounwind {
905; ALL-LABEL: ult_f64:
906
907; 32-C-DAG:      addiu $2, $zero, 1
908; 32-C-DAG:      c.ult.d $f12, $f14
909; 32-C:          movf $2, $zero, $fcc0
910
911; 64-C-DAG:      addiu $2, $zero, 1
912; 64-C-DAG:      c.ult.d $f12, $f13
913; 64-C:          movf $2, $zero, $fcc0
914
915; 32-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
916; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
917; 32-CMP-DAG:    andi $2, $[[T1]], 1
918
919; 64-CMP-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
920; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
921; 64-CMP-DAG:    andi $2, $[[T1]], 1
922
923; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
924; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
925; MM32R3-DAG:    c.ult.d $f12, $f14
926; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
927
928; MM32R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f14
929; MM64R6-DAG:    cmp.ult.d $[[T0:f[0-9]+]], $f12, $f13
930; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
931; MMR6-DAG:      andi16 $2, $[[T1]], 1
932
933  %1 = fcmp ult double %a, %b
934  %2 = zext i1 %1 to i32
935  ret i32 %2
936}
937
938define i32 @ule_f64(double %a, double %b) nounwind {
939; ALL-LABEL: ule_f64:
940
941; 32-C-DAG:      addiu $2, $zero, 1
942; 32-C-DAG:      c.ule.d $f12, $f14
943; 32-C:          movf $2, $zero, $fcc0
944
945; 64-C-DAG:      addiu $2, $zero, 1
946; 64-C-DAG:      c.ule.d $f12, $f13
947; 64-C:          movf $2, $zero, $fcc0
948
949; 32-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
950; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
951; 32-CMP-DAG:    andi $2, $[[T1]], 1
952
953; 64-CMP-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
954; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
955; 64-CMP-DAG:    andi $2, $[[T1]], 1
956
957; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
958; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
959; MM32R3-DAG:    c.ule.d $f12, $f14
960; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
961
962; MM32R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f14
963; MM64R6-DAG:    cmp.ule.d $[[T0:f[0-9]+]], $f12, $f13
964; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
965; MMR6-DAG:      andi16 $2, $[[T1]], 1
966
967  %1 = fcmp ule double %a, %b
968  %2 = zext i1 %1 to i32
969  ret i32 %2
970}
971
972define i32 @une_f64(double %a, double %b) nounwind {
973; ALL-LABEL: une_f64:
974
975; 32-C-DAG:      addiu $2, $zero, 1
976; 32-C-DAG:      c.eq.d $f12, $f14
977; 32-C:          movt $2, $zero, $fcc0
978
979; 64-C-DAG:      addiu $2, $zero, 1
980; 64-C-DAG:      c.eq.d $f12, $f13
981; 64-C:          movt $2, $zero, $fcc0
982
983; 32-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
984; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
985; 32-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
986; 32-CMP-DAG:    andi $2, $[[T2]], 1
987
988; 64-CMP-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
989; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
990; 64-CMP-DAG:    not $[[T2:[0-9]+]], $[[T1]]
991; 64-CMP-DAG:    andi $2, $[[T2]], 1
992
993; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
994; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
995; MM32R3-DAG:    c.eq.d  $f12, $f14
996; MM32R3-DAG:    movt $[[T1]], $[[T0]], $fcc0
997
998; MM32R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f14
999; MM64R6-DAG:    cmp.eq.d $[[T0:f[0-9]+]], $f12, $f13
1000; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
1001; MMR6-DAG:      not $[[T2:[0-9]+]], $[[T1]]
1002; MMR6-DAG:      andi16 $2, $[[T2]], 1
1003
1004  %1 = fcmp une double %a, %b
1005  %2 = zext i1 %1 to i32
1006  ret i32 %2
1007}
1008
1009define i32 @uno_f64(double %a, double %b) nounwind {
1010; ALL-LABEL: uno_f64:
1011
1012; 32-C-DAG:      addiu $2, $zero, 1
1013; 32-C-DAG:      c.un.d $f12, $f14
1014; 32-C:          movf $2, $zero, $fcc0
1015
1016; 64-C-DAG:      addiu $2, $zero, 1
1017; 64-C-DAG:      c.un.d $f12, $f13
1018; 64-C:          movf $2, $zero, $fcc0
1019
1020; 32-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
1021; 32-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
1022; 32-CMP-DAG:    andi $2, $[[T1]], 1
1023
1024; 64-CMP-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
1025; 64-CMP-DAG:    mfc1 $[[T1:[0-9]+]], $[[T0]]
1026; 64-CMP-DAG:    andi $2, $[[T1]], 1
1027
1028; MM32R3-DAG:    lui $[[T0:[0-9]+]], 0
1029; MM32R3-DAG:    li16 $[[T1:[0-9]+]], 1
1030; MM32R3-DAG:    c.un.d $f12, $f14
1031; MM32R3-DAG:    movf $[[T1]], $[[T0]], $fcc0
1032
1033; MM32R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f14
1034; MM64R6-DAG:    cmp.un.d $[[T0:f[0-9]+]], $f12, $f13
1035; MMR6-DAG:      mfc1 $[[T1:[0-9]+]], $[[T0]]
1036; MMR6-DAG:      andi16 $2, $[[T1]], 1
1037
1038  %1 = fcmp uno double %a, %b
1039  %2 = zext i1 %1 to i32
1040  ret i32 %2
1041}
1042
1043define i32 @true_f64(double %a, double %b) nounwind {
1044; ALL-LABEL: true_f64:
1045; 32-C:          addiu $2, $zero, 1
1046
1047; 32-CMP:        addiu $2, $zero, 1
1048
1049; 64-C:          addiu $2, $zero, 1
1050
1051; 64-CMP:        addiu $2, $zero, 1
1052
1053; MM-DAG:        li16 $2, 1
1054
1055  %1 = fcmp true double %a, %b
1056  %2 = zext i1 %1 to i32
1057  ret i32 %2
1058}
1059
1060; The optimizers sometimes produce setlt instead of setolt/setult.
1061define float @bug1_f32(float %angle, float %at) #0 {
1062entry:
1063; ALL-LABEL: bug1_f32:
1064
1065; 32-C-DAG:      add.s    $[[T0:f[0-9]+]], $f14, $f12
1066; 32-C-DAG:      lwc1     $[[T1:f[0-9]+]], %lo($CPI32_0)(
1067; 32-C-DAG:      c.ole.s  $[[T0]], $[[T1]]
1068; 32-C-DAG:      bc1t
1069
1070; 32-CMP-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1071; 32-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %lo($CPI32_0)(
1072; 32-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1073; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1074; FIXME: This instruction is redundant.
1075; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1076; 32-CMP-DAG:    bnezc    $[[T4]],
1077
1078; 64-C-DAG:      add.s    $[[T0:f[0-9]+]], $f13, $f12
1079; 64-C-DAG:      lwc1     $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
1080; 64-C-DAG:      c.ole.s  $[[T0]], $[[T1]]
1081; 64-C-DAG:      bc1t
1082
1083; 64-CMP-DAG:    add.s    $[[T0:f[0-9]+]], $f13, $f12
1084; 64-CMP-DAG:    lwc1     $[[T1:f[0-9]+]], %got_ofst($CPI32_0)(
1085; 64-CMP-DAG:    cmp.le.s $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1086; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1087; FIXME: This instruction is redundant.
1088; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1089; 64-CMP-DAG:    bnezc    $[[T4]],
1090
1091; MM32R3-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1092; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
1093; MM32R3-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1094; MM32R3-DAG:    c.ole.s  $[[T0]], $[[T2]]
1095; MM32R3-DAG:    bc1t
1096
1097; MM32R6-DAG:    add.s    $[[T0:f[0-9]+]], $f14, $f12
1098; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI32_0)
1099; MM32R6-DAG:    lwc1     $[[T2:f[0-9]+]], %lo($CPI32_0)($[[T1]])
1100; MM32R6-DAG:    cmp.le.s $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1101; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3:f[0-9]+]]
1102; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
1103; MM32R6-DAG:    bnez     $[[T5]],
1104
1105; MM64R6-DAG:    lui      $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f32)))
1106; MM64R6-DAG:    daddu    $[[T1:[0-9]+]], $[[T0]], $25
1107; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f32)))
1108; MM64R6-DAG:    add.s    $[[T3:f[0-9]+]], $f13, $f12
1109; MM64R6-DAG:    ld       $[[T4:[0-9]+]], %got_page($CPI32_0)($[[T2]])
1110; MM64R6-DAG:    lwc1     $[[T5:f[0-9]+]], %got_ofst($CPI32_0)($[[T4]])
1111; MM64R6-DAG:    cmp.le.s $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
1112; MM64R6-DAG:    mfc1     $[[T7:[0-9]+]], $[[T6]]
1113; MM64R6-DAG:    andi16   $[[T8:[0-9]+]], $[[T7]], 1
1114; MM64R6-DAG:    bnez     $[[T8]],
1115
1116  %add = fadd fast float %at, %angle
1117  %cmp = fcmp ogt float %add, 1.000000e+00
1118  br i1 %cmp, label %if.then, label %if.end
1119
1120if.then:
1121  %sub = fadd fast float %add, -1.000000e+00
1122  br label %if.end
1123
1124if.end:
1125  %theta.0 = phi float [ %sub, %if.then ], [ %add, %entry ]
1126  ret float %theta.0
1127}
1128
1129; The optimizers sometimes produce setlt instead of setolt/setult.
1130define double @bug1_f64(double %angle, double %at) #0 {
1131entry:
1132; ALL-LABEL: bug1_f64:
1133
1134; 32-C-DAG:      add.d    $[[T0:f[0-9]+]], $f14, $f12
1135; 32-C-DAG:      ldc1     $[[T1:f[0-9]+]], %lo($CPI33_0)(
1136; 32-C-DAG:      c.ole.d  $[[T0]], $[[T1]]
1137; 32-C-DAG:      bc1t
1138
1139; 32-CMP-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1140; 32-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %lo($CPI33_0)(
1141; 32-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1142; 32-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1143; FIXME: This instruction is redundant.
1144; 32-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1145; 32-CMP-DAG:    bnezc    $[[T4]],
1146
1147; 64-C-DAG:      add.d    $[[T0:f[0-9]+]], $f13, $f12
1148; 64-C-DAG:      ldc1     $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
1149; 64-C-DAG:      c.ole.d  $[[T0]], $[[T1]]
1150; 64-C-DAG:      bc1t
1151
1152; 64-CMP-DAG:    add.d    $[[T0:f[0-9]+]], $f13, $f12
1153; 64-CMP-DAG:    ldc1     $[[T1:f[0-9]+]], %got_ofst($CPI33_0)(
1154; 64-CMP-DAG:    cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
1155; 64-CMP-DAG:    mfc1     $[[T3:[0-9]+]], $[[T2]]
1156; FIXME: This instruction is redundant.
1157; 64-CMP-DAG:    andi     $[[T4:[0-9]+]], $[[T3]], 1
1158; 64-CMP-DAG:    bnezc    $[[T4]],
1159
1160; MM32R3-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1161; MM32R3-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
1162; MM32R3-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1163; MM32R3-DAG:    c.ole.d  $[[T0]], $[[T2]]
1164; MM32R3-DAG:    bc1t
1165
1166; MM32R6-DAG:    add.d    $[[T0:f[0-9]+]], $f14, $f12
1167; MM32R6-DAG:    lui      $[[T1:[0-9]+]], %hi($CPI33_0)
1168; MM32R6-DAG:    ldc1     $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
1169; MM32R6-DAG:    cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
1170; MM32R6-DAG:    mfc1     $[[T4:[0-9]+]], $[[T3]]
1171; MM32R6-DAG:    andi16   $[[T5:[0-9]+]], $[[T4]], 1
1172; MM32R6-DAG:    bnez     $[[T5]],
1173
1174; MM64R6-DAG:    lui      $[[T0:[0-9]+]], %hi(%neg(%gp_rel(bug1_f64)))
1175; MM64R6-DAG:    daddu    $[[T1:[0-9]+]], $[[T0]], $25
1176; MM64R6-DAG:    daddiu   $[[T2:[0-9]+]], $[[T1]], %lo(%neg(%gp_rel(bug1_f64)))
1177; MM64R6-DAG:    add.d    $[[T3:f[0-9]+]], $f13, $f12
1178; MM64R6-DAG:    ld       $[[T4:[0-9]+]], %got_page($CPI33_0)($[[T2]])
1179; MM64R6-DAG:    ldc1     $[[T5:f[0-9]+]], %got_ofst($CPI33_0)($[[T4]])
1180; MM64R6-DAG:    cmp.le.d $[[T6:f[0-9]+]], $[[T3]], $[[T5]]
1181; MM64R6-DAG:    mfc1     $[[T7:[0-9]+]], $[[T6]]
1182; MM64R6-DAG:    andi16   $[[T8:[0-9]+]], $[[T7]], 1
1183; MM64R6-DAG:    bnez     $[[T8]],
1184
1185  %add = fadd fast double %at, %angle
1186  %cmp = fcmp ogt double %add, 1.000000e+00
1187  br i1 %cmp, label %if.then, label %if.end
1188
1189if.then:
1190  %sub = fadd fast double %add, -1.000000e+00
1191  br label %if.end
1192
1193if.end:
1194  %theta.0 = phi double [ %sub, %if.then ], [ %add, %entry ]
1195  ret double %theta.0
1196}
1197
1198attributes #0 = { nounwind readnone "no-nans-fp-math"="true" }
1199