| /external/llvm/test/CodeGen/Mips/ |
| D | atomic.ll | 46 ; MICROMIPS: beqzc $[[R4]], $[[BB0]]
47 ; MIPSR6: beqzc $[[R4]], $[[BB0]]
68 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
69 ; MIPSR6: beqzc $[[R2]], $[[BB0]]
89 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
90 ; MIPSR6: beqzc $[[R2]], $[[BB0]]
114 ; MICROMIPS: beqzc $[[R2]], $[[BB0]]
115 ; MIPSR6: beqzc $[[R2]], $[[BB0]]
156 ; MICROMIPS: beqzc $[[R16]], $[[BB0]]
157 ; MIPSR6: beqzc $[[R16]], $[[BB0]]
[all …]
|
| D | micromips-atomic.ll | 17 ; CHECK: beqzc $[[R2]], $[[BB0]]
|
| D | fpbr.ll | 86 ; 64-GPR: beqzc $[[GPRCC]], $BB2_2
177 ; 64-GPR: beqzc $[[GPRCC]], $BB5_2
|
| D | analyzebranch.ll | 53 ; 64-GPR beqzc $[[GPRCC]], $BB
|
| /external/llvm/test/CodeGen/Mips/compactbranches/ |
| D | compact-branch-policy.ll | 12 ; ALWAYS: beqzc
14 ; immediately following beqzc would cause a forbidden slot hazard.
|
| D | no-beqzc-bnezc.ll | 5 ; bnezc and beqzc have restriction that $rt != 0
23 ; CHECK-NOT: beqzc $0
|
| D | compact-branches.ll | 169 ; CHECK: beqzc
194 ; CHECK: beqzc
|
| D | beqc-bnec-register-constraint.ll | 4 ; Cases where $rs == 0 and $rt != 0 should be transformed into beqzc/bnezc.
|
| /external/llvm/test/MC/Mips/micromips32r6/ |
| D | relocations.s | 20 # CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
42 beqzc $3, bar
|
| D | valid.s | 35 beqzc $3, 64 # CHECK: beqzc $3, 64 # encoding: [0x80,0x60,0x00,0x20]
|
| /external/llvm/test/MC/Mips/micromips64r6/ |
| D | relocations.s | 23 # CHECK-FIXUP: beqzc $3, bar # encoding: [0x80,0b011AAAAA,A,A]
47 beqzc $3, bar
|
| /external/llvm/test/MC/Mips/mips32r6/ |
| D | relocations.s | 17 # CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
63 beqzc $9, bar
|
| /external/llvm/test/MC/Mips/mips64r6/ |
| D | relocations.s | 17 # CHECK-FIXUP: beqzc $9, bar # encoding: [0xd9,0b001AAAAA,A,A]
68 beqzc $9, bar
|
| /external/llvm/test/MC/Mips/ |
| D | relocation.s | 224 beqzc $2, foo // RELOC: R_MIPS_PC21_S2 foo
|
| /external/llvm/test/MC/Disassembler/Mips/mips64r6/ |
| D | valid-mips64r6-el.txt | 22 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
23 0xfa 0xff 0x5f 0xd8 # CHECK: beqzc $2, -20
|
| D | valid-mips64r6.txt | 205 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
206 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
|
| /external/llvm/test/MC/Disassembler/Mips/mips32r6/ |
| D | valid-mips32r6.txt | 181 0xd8 0xa0 0x46 0x90 # CHECK: beqzc $5, 72260
182 0xd8 0x5f 0xff 0xfa # CHECK: beqzc $2, -20
|
| D | valid-mips32r6-el.txt | 25 0x90 0x46 0xa0 0xd8 # CHECK: beqzc $5, 72260
|
| /external/v8/src/mips/ |
| D | assembler-mips.h | 681 void beqzc(Register rs, int32_t offset);
682 inline void beqzc(Register rs, Label* L) { in beqzc() function
683 beqzc(rs, shifted_branch_offset21(L)); in beqzc()
|
| /external/v8/src/mips64/ |
| D | assembler-mips64.h | 685 void beqzc(Register rs, int32_t offset);
686 inline void beqzc(Register rs, Label* L) { in beqzc() function
687 beqzc(rs, shifted_branch_offset21(L)); in beqzc()
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r3/ |
| D | valid.txt | 158 0x40 0xe9 0x02 0x9a # CHECK: beqzc $9, 1332
|
| D | valid-el.txt | 158 0xe9 0x40 0x9a 0x02 # CHECK: beqzc $9, 1332
|
| /external/llvm/lib/Target/Mips/ |
| D | MicroMips32r6InstrInfo.td | 57 class BEQZC_MMR6_ENC : CMP_BRANCH_OFF21_FM_MMR6<"beqzc", 0b100000>;
1249 : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21_mm, GPR32Opnd>,
1250 MMR6Arch<"beqzc">;
|
| D | MipsSchedule.td | 52 def II_BCCZC : InstrItinClass; // beqzc, bnezc
|
| /external/llvm/test/MC/Disassembler/Mips/micromips32r6/ |
| D | valid.txt | 54 0x80 0x60 0x00 0x20 # CHECK: beqzc $3, 64
|