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Searched refs:bgezall (Results 1 – 25 of 37) sorted by relevance

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/external/valgrind/none/tests/mips32/
Dbranches.stdout.exp264 bgezall :: 4, RSval: 0
265 bgezall :: 5, RSval: 1
266 bgezall :: 8, RSval: -1
267 bgezall :: 9, RSval: -1
268 bgezall :: 10, RSval: -2
269 bgezall :: 11, RSval: -1
270 bgezall :: 10, RSval: 5
271 bgezall :: 13, RSval: -3
272 bgezall :: 12, RSval: 125
273 bgezall :: 15, RSval: -2147483648
[all …]
/external/valgrind/none/tests/mips64/
Dbranches.stdout.exp264 bgezall :: out: 4, RDval: 0, RSval: 0
265 bgezall :: out: 5, RDval: 1, RSval: 1
266 bgezall :: out: 8, RDval: 2, RSval: -1
267 bgezall :: out: 9, RDval: 3, RSval: -1
268 bgezall :: out: 10, RDval: 4, RSval: -2
269 bgezall :: out: 11, RDval: 5, RSval: -1
270 bgezall :: out: 10, RDval: 6, RSval: 5
271 bgezall :: out: 13, RDval: 7, RSval: -3
272 bgezall :: out: 12, RDval: 8, RSval: 125
273 bgezall :: out: 15, RDval: 9, RSval: -2147483648
[all …]
/external/llvm/test/MC/Mips/
Dmips-jump-delay-slots.s92 # CHECK: bgezall $6, 1332
94 bgezall $6,1332
/external/llvm/test/MC/Mips/mips2/
Dvalid.s32bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r6/
Dinvalid-mips2.s19bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips64r6/
Dinvalid-mips2.s16bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/external/llvm/test/MC/Mips/mips32r3/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips3/
Dvalid.s32bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r5/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips32r2/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips1/
Dinvalid-mips2.s13bgezall $12,7293 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/external/llvm/test/MC/Mips/mips5/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips4/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r3/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r2/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/llvm/test/MC/Mips/mips64r5/
Dvalid.s36bgezall $12,7293 # CHECK: bgezall $12, 7293 # encoding: [0x05,0x93,0x07,0x1f]
/external/v8/src/mips/
Dassembler-mips.h633 void bgezall(Register rs, int16_t offset);
634 inline void bgezall(Register rs, Label* L) { in bgezall() function
635 bgezall(rs, branch_offset(L) >> 2); in bgezall()
/external/v8/src/mips64/
Dassembler-mips64.h637 void bgezall(Register rs, int16_t offset);
638 inline void bgezall(Register rs, Label* L) { in bgezall() function
639 bgezall(rs, branch_offset(L) >> 2); in bgezall()
/external/llvm/test/MC/Disassembler/Mips/mips2/
Dvalid-mips2-el.txt25 0x1f 0x07 0x93 0x05 # CHECK: bgezall $12, 7296
Dvalid-mips2.txt76 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296
/external/llvm/test/MC/Disassembler/Mips/mips3/
Dvalid-mips3-el.txt25 0x1f 0x07 0x93 0x05 # CHECK: bgezall $12, 7296
Dvalid-mips3.txt107 0x05 0x93 0x07 0x1f # CHECK: bgezall $12, 7296
/external/llvm/test/MC/Disassembler/Mips/mips4/
Dvalid-mips4-el.txt29 0x1f 0x07 0x93 0x05 # CHECK: bgezall $12, 7296

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