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Searched refs:cmask (Results 1 – 19 of 19) sorted by relevance

/external/valgrind/tests/
Dx86_amd64_features.c73 unsigned int level = 0, cmask = 0, dmask = 0, a, b, c, d; in go() local
96 cmask = 1 << 0; in go()
99 cmask = 1 << 9; in go()
102 cmask = 1 << 5; in go()
107 cmask = 1 << 0; in go()
110 cmask = 1 << 1; in go()
113 cmask = 1 << 9; in go()
116 cmask = 1 << 13; in go()
119 cmask = 1 << 5; in go()
123 cmask = 1 << 20; in go()
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/external/mesa3d/src/gallium/drivers/nouveau/nv30/
Dnv30_state.c44 uint32_t blend[2], cmask[2]; in nv30_blend_state_create() local
65 cmask[0] = !!(cso->rt[0].colormask & PIPE_MASK_A) << 24 | in nv30_blend_state_create()
71 cmask[1] = 0; in nv30_blend_state_create()
74 cmask[1] |= !!(cso->rt[i].colormask & PIPE_MASK_A) << (0 + (i * 4)) | in nv30_blend_state_create()
81 cmask[1] = 0x00001110 * !!(cmask[0] & 0x01000000); in nv30_blend_state_create()
82 cmask[1] |= 0x00002220 * !!(cmask[0] & 0x00010000); in nv30_blend_state_create()
83 cmask[1] |= 0x00004440 * !!(cmask[0] & 0x00000100); in nv30_blend_state_create()
84 cmask[1] |= 0x00008880 * !!(cmask[0] & 0x00000001); in nv30_blend_state_create()
90 SB_DATA (so, cmask[1]); in nv30_blend_state_create()
114 SB_DATA (so, cmask[0]); in nv30_blend_state_create()
/external/mesa3d/src/gallium/drivers/radeon/
Dr600_texture.c84 if (rdst->cmask.size && rdst->dirty_level_mask & (1 << dst_level)) { in r600_prepare_for_dma_blit()
96 if (rsrc->cmask.size && rsrc->dirty_level_mask & (1 << src_level)) in r600_prepare_for_dma_blit()
325 if (!rtex->cmask.size) in r600_texture_discard_cmask()
331 memset(&rtex->cmask, 0, sizeof(rtex->cmask)); in r600_texture_discard_cmask()
332 rtex->cmask.base_address_reg = rtex->resource.gpu_address >> 8; in r600_texture_discard_cmask()
473 rtex->cmask = new_tex->cmask; /* needed even without CMASK */ in r600_degrade_tile_mode_to_linear()
476 assert(!rtex->cmask.size); in r600_degrade_tile_mode_to_linear()
519 (rtex->cmask.size || rtex->dcc_offset)) { in r600_texture_get_handle()
526 if (rtex->cmask.size) in r600_texture_get_handle()
743 si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask); in r600_texture_allocate_cmask()
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Dr600_pipe_common.h257 struct r600_cmask_info cmask; member
/external/mesa3d/src/amd/vulkan/
Dradv_image.c569 radv_image_get_cmask_info(device, image, &image->cmask); in radv_image_alloc_cmask()
571 image->cmask.offset = align64(image->size, image->cmask.alignment); in radv_image_alloc_cmask()
573 image->clear_value_offset = image->cmask.offset + image->cmask.size; in radv_image_alloc_cmask()
574 image->size = image->cmask.offset + image->cmask.size + 8; in radv_image_alloc_cmask()
575 image->alignment = MAX2(image->alignment, image->cmask.alignment); in radv_image_alloc_cmask()
Dradv_meta_clear.c841 if (!iview->image->cmask.size && !iview->image->surface.dcc_size) in emit_fast_color_clear()
897 iview->image->offset + iview->image->cmask.offset, in emit_fast_color_clear()
898 iview->image->cmask.size, 0); in emit_fast_color_clear()
Dradv_cmd_buffer.c813 if (!image->cmask.size && !image->surface.dcc_size) in radv_set_color_clear_regs()
840 if (!image->cmask.size && !image->surface.dcc_size) in radv_load_color_clear_regs()
2430 radv_fill_buffer(cmd_buffer, image->bo, image->offset + image->cmask.offset, in radv_initialise_cmask()
2431 image->cmask.size, value); in radv_initialise_cmask()
2526 if (image->cmask.size) in radv_handle_image_transition()
Dradv_device.c1603 va += iview->image->cmask.offset; in radv_initialise_color_surface()
1605 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max; in radv_initialise_color_surface()
1695 if (iview->image->cmask.size && in radv_initialise_color_surface()
Dradv_private.h1033 struct radv_cmask_info cmask; member
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_blit.c490 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_sampler_color_textures()
517 if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset) in si_decompress_image_color_textures()
819 } else if (rtex->fmask.size || rtex->cmask.size || rtex->dcc_offset) { in si_decompress_subresource()
1020 (!dst->cmask.size || !dst->dirty_level_mask)) { /* dst cannot be fast-cleared */ in do_hardware_msaa_resolve()
1205 if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) { in si_flush_resource()
Dsi_state.c2593 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ in si_emit_framebuffer_state()
2594 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ in si_emit_framebuffer_state()
Dsi_descriptors.c495 return rtex->cmask.size || rtex->fmask.size || in is_compressed_colortex()
/external/mesa3d/src/gallium/drivers/r600/
Dr600_blit.c355 assert(tex->cmask.size); in r600_decompress_color_textures()
394 } else if (rtex->cmask.size) { in r600_decompress_subresource()
796 (!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) { in do_hardware_msaa_resolve()
904 if (!rtex->is_depth && rtex->cmask.size) { in r600_flush_resource()
Dr600_state.c949 if (rtex->cmask.size) { in r600_init_color_surface()
950 surf->cb_color_cmask = rtex->cmask.offset >> 8; in r600_init_color_surface()
951 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask.slice_tile_max); in r600_init_color_surface()
967 struct r600_cmask_info cmask; in r600_init_color_surface() local
970 r600_texture_get_cmask_info(&rscreen->b, rtex, &cmask); in r600_init_color_surface()
975 rctx->dummy_cmask->b.b.width0 < cmask.size || in r600_init_color_surface()
976 rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) { in r600_init_color_surface()
984 cmask.size, cmask.alignment); in r600_init_color_surface()
988 memset(ptr, 0xCC, cmask.size); in r600_init_color_surface()
1009 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) | in r600_init_color_surface()
Dr600_state_common.c651 if (!is_buffer && rtex->cmask.size) { in r600_set_sampler_views()
701 if (rtex->cmask.size) { in r600_update_compressed_colortex_mask()
Devergreen_state.c1567 radeon_emit(cs, tex->cmask.base_address_reg); /* R_028C7C_CB_COLOR0_CMASK */ in evergreen_emit_framebuffer_state()
1568 radeon_emit(cs, tex->cmask.slice_tile_max); /* R_028C80_CB_COLOR0_CMASK_SLICE */ in evergreen_emit_framebuffer_state()
/external/kernel-headers/original/uapi/sound/
Dasound.h390 unsigned int cmask; /* R: changed masks */ member
/external/tinyalsa/
Dpcm.c237 p->cmask = 0; in param_init()
/external/mesa3d/src/gallium/drivers/svga/
Dsvga_tgsi_vgpu10.c3234 unsigned cmask = plane_mask & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; in emit_clip_distance_declarations() local
3236 VGPU10_NAME_CLIP_DISTANCE, cmask); in emit_clip_distance_declarations()
3240 unsigned cmask = (plane_mask >> 4) & VGPU10_OPERAND_4_COMPONENT_MASK_ALL; in emit_clip_distance_declarations() local
3242 VGPU10_NAME_CLIP_DISTANCE, cmask); in emit_clip_distance_declarations()