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Searched refs:coalesce (Results 1 – 25 of 40) sorted by relevance

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/external/mesa3d/src/gallium/drivers/etnaviv/
Detnaviv_emit.c80 struct etna_coalesce *coalesce) in etna_coalesce_start() argument
82 coalesce->start = etna_cmd_stream_offset(stream); in etna_coalesce_start()
83 coalesce->last_reg = 0; in etna_coalesce_start()
84 coalesce->last_fixp = 0; in etna_coalesce_start()
89 struct etna_coalesce *coalesce) in etna_coalesce_end() argument
92 uint32_t size = end - coalesce->start; in etna_coalesce_end()
95 uint32_t offset = coalesce->start - 1; in etna_coalesce_end()
108 check_coalsence(struct etna_cmd_stream *stream, struct etna_coalesce *coalesce, in check_coalsence() argument
111 if (coalesce->last_reg != 0) { in check_coalsence()
112 if (((coalesce->last_reg + 4) != reg) || (coalesce->last_fixp != fixp)) { in check_coalsence()
[all …]
/external/iw/
Dcoalesce.c17 SECTION(coalesce);
168 COMMAND(coalesce, enable, "<config-file>",
195 COMMAND(coalesce, disable, "", NL80211_CMD_SET_COALESCE, 0, CIB_PHY,
286 COMMAND(coalesce, show, "", NL80211_CMD_GET_COALESCE, 0, CIB_PHY, handle_coalesce_show,
DAndroid.mk10 bitrate.c wowlan.c coalesce.c roc.c p2p.c vendor.c \
DMakefile19 bitrate.o wowlan.o coalesce.o roc.o p2p.o vendor.o
/external/llvm/test/CodeGen/ARM/
D2012-10-04-AAPCS-byval-align8.ll31 ; ldm is not formed when the coalescer failed to coalesce everything.
58 ; ldm is not formed when the coalescer failed to coalesce everything.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
Dsubreg-to-reg-3.ll3 ; Don't eliminate or coalesce away the explicit zero-extension!
D2004-04-09-SameValueCoalescing.ll1 ; Linear scan does not currently coalesce any two variables that have
Dsubreg-to-reg-1.ll3 ; Don't eliminate or coalesce away the explicit zero-extension!
Doverlap-shift.ll2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
Dcoalesce-esp.ll4 ; Don't coalesce with %esp if it would end up putting %esp in
Dtwoaddr-lea.ll2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
D2009-08-06-inlineasm.ll5 ; FIXME: If the coalescer happens to coalesce %level.1 with the copy to EAX
/external/llvm/test/CodeGen/X86/
Dsubreg-to-reg-3.ll5 ; Don't eliminate or coalesce away the explicit zero-extension!
Dsubreg-to-reg-1.ll6 ; Don't eliminate or coalesce away the explicit zero-extension!
Doverlap-shift.ll2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
Dcse-add-with-overflow.ll5 ; MachineCSE should coalesce trivial subregister copies.
Dtwoaddr-lea.ll2 ;; cannot coalesce it with Y. Because of this, a copy needs to be
Dcoalesce-esp.ll4 ; Don't coalesce with %esp if it would end up putting %esp in
D2009-08-06-inlineasm.ll5 ; FIXME: If the coalescer happens to coalesce %level.1 with the copy to EAX
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_util.cpp135 r->coalesce(&tail); in extend()
140 r->coalesce(&tail); in extend()
Dnv50_ir_util.h457 void coalesce(Range **ptail) in coalesce() function
/external/llvm/test/CodeGen/PowerPC/
Dtls-store2.ll27 ; initial scheduling, but don't coalesce it again after we move the instructions
/external/jemalloc/include/jemalloc/internal/
Djemalloc_internal_defs.h.in195 * automatically coalesce, and they fragment when changes are made to subranges.
198 * mappings do *not* coalesce/fragment.
/external/llvm/test/CodeGen/AArch64/GlobalISel/
Darm64-regbankselect.mir253 # Greedy mode coalesce the computation on the GPR register
299 # Greedy mode coalesce the computation on the GPR register because it
/external/llvm/test/Transforms/LoopStrengthReduce/ARM/
D2012-06-15-lsr-noaddrmode.ll8 ; to coalesce the IV. See <rdar://problem/11680670> [coalescer] IVs

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