| /external/swiftshader/third_party/LLVM/lib/Target/ |
| D | TargetInstrInfo.cpp | 54 unsigned Class = MI->getDesc().getSchedClass(); in getNumMicroOps()
71 unsigned DefClass = DefMI->getDesc().getSchedClass(); in getOperandLatency()
72 unsigned UseClass = UseMI->getDesc().getSchedClass(); in getOperandLatency()
86 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
89 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
99 return ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrLatency()
110 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
119 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
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| /external/llvm/lib/CodeGen/ |
| D | TargetSchedule.cpp | 79 int UOps = InstrItins.getNumMicroOps(MI->getDesc().getSchedClass()); in getNumMicroOps()
105 unsigned SchedClass = MI->getDesc().getSchedClass(); in resolveSchedClass()
168 unsigned DefClass = DefMI->getDesc().getSchedClass(); in computeOperandLatency()
241 unsigned SCIdx = TII->get(Opcode).getSchedClass(); in computeInstrLatency()
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| D | TargetInstrInfo.cpp | 990 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
993 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass(); in getOperandLatency()
1005 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass()); in getInstrLatency()
1017 unsigned Class = MI.getDesc().getSchedClass(); in getNumMicroOps()
1051 return ItinData->getStageLatency(MI.getDesc().getSchedClass()); in getInstrLatency()
1061 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
1073 unsigned DefClass = DefMI.getDesc().getSchedClass(); in getOperandLatency()
1074 unsigned UseClass = UseMI.getDesc().getSchedClass(); in getOperandLatency()
1108 unsigned DefClass = DefMI.getDesc().getSchedClass(); in computeOperandLatency()
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| D | ScoreboardHazardRecognizer.cpp | 125 unsigned idx = MCID->getSchedClass(); in getHazardType()
185 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
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| D | DFAPacketizer.cpp | 120 unsigned InsnClass = MID->getSchedClass(); in canReserveResources()
131 unsigned InsnClass = MID->getSchedClass(); in reserveResources()
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| D | MachineCombiner.cpp | 296 unsigned Idx = TII->get(Opc).getSchedClass(); in instr2instrSC()
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| D | MachineScheduler.cpp | 1793 const MCSchedClassDesc *SC = DAG->getSchedClass(&*I); in init()
1874 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in checkHazard()
2077 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in bumpNode()
2306 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); in initResourceDelta()
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | ScoreboardHazardRecognizer.cpp | 123 unsigned idx = MCID->getSchedClass(); in getHazardType()
185 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
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| D | ScheduleDAGInstrs.cpp | 633 unsigned DefClass = DefMI->getDesc().getSchedClass(); in ComputeOperandLatency()
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 167 unsigned SCClass = Desc.getSchedClass(); in getItineraryLatency()
194 unsigned SCClass = Desc.getSchedClass(); in getLatency()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
92 unsigned IIC = MCID->getSchedClass(); in mustComeFirst()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 81 unsigned SCIdx = TII->get(AArch64::STPDi).getSchedClass(); in shouldAddSTPToBlock()
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| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| D | SPUNopFiller.cpp | 139 int sc = instr.getDesc().getSchedClass(); in getOpPlacement()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenSchedule.h | 349 CodeGenSchedClass &getSchedClass(unsigned Idx) { in getSchedClass() function
353 const CodeGenSchedClass &getSchedClass(unsigned Idx) const { in getSchedClass() function
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| D | SubtargetEmitter.cpp | 578 ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; in EmitItineraries()
1120 assert(SchedModels.getSchedClass(0).Name == "NoInstrModel" in EmitSchedClassTables()
1128 const CodeGenSchedClass &SchedClass = SchedModels.getSchedClass(SCIdx); in EmitSchedClassTables()
1291 const CodeGenSchedClass &SC = SchedModels.getSchedClass(VC); in EmitSchedModelHelpers()
1321 << SchedModels.getSchedClass(T.ToClassIdx).Name << '\n'; in EmitSchedModelHelpers()
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| D | CodeGenSchedule.cpp | 540 CodeGenSchedClass &SC = getSchedClass(SCIdx); in collectSchedClasses()
1329 SchedModels.getSchedClass(FromClassIdx).Transitions.push_back(SCTrans); in inferFromTransitions()
1568 const CodeGenSchedClass &SC = getSchedClass(SCIdx); in checkCompleteness()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 269 unsigned getSchedClass() const { in getSchedClass() function
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 528 unsigned getSchedClass() const { return SchedClass; } in getSchedClass() function
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 246 const MCSchedClassDesc *getSchedClass(SUnit *SU) const { in getSchedClass() function
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 1982 unsigned Class = Desc.getSchedClass(); in getNumMicroOps()
2232 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency()
2233 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency()
2512 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
2680 unsigned Class = MCID.getSchedClass(); in getInstrLatency()
2702 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
2737 unsigned DefClass = DefMI->getDesc().getSchedClass(); in hasLowDefLatency()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.cpp | 2041 unsigned SchedClass = MI->getDesc().getSchedClass(); in isEarlySourceInstr()
2251 unsigned SchedClass = MI->getDesc().getSchedClass(); in isLateResultInstr()
2279 return MI->getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE; in isLateSourceInstr()
2548 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC1()
2567 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC2()
2584 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC2Early()
2608 unsigned SchedClass = MI->getDesc().getSchedClass(); in isTC4x()
4008 unsigned Latency = ItinData->getStageLatency(MI->getDesc().getSchedClass()); in getInstrTimingClassLatency()
4183 const InstrStage &IS = *II.beginStage(MI->getDesc().getSchedClass()); in getUnits()
4260 " Class: " << NewMI->getDesc().getSchedClass()); in genAllInsnTimingClasses()
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| D | HexagonVLIWPacketizer.cpp | 938 auto *IS = ResourceTracker->getInstrItins()->beginStage(TID.getSchedClass()); in ignorePseudoInstruction()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 380 int SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in getUnits()
728 unsigned SchedClass = HexagonMCInstrInfo::getDesc(MCII, MCI).getSchedClass(); in prefersSlot3()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 2778 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass()); in getNumMicroOpsSwiftLdSt()
3076 unsigned Class = Desc.getSchedClass(); in getNumMicroOps()
3334 unsigned DefClass = DefMCID.getSchedClass(); in getOperandLatency()
3335 unsigned UseClass = UseMCID.getSchedClass(); in getOperandLatency()
3785 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx); in getOperandLatency()
4034 unsigned Class = MCID.getSchedClass(); in getInstrLatency()
4064 return ItinData->getStageLatency(get(Opcode).getSchedClass()); in getInstrLatency()
4101 unsigned DefClass = DefMI.getDesc().getSchedClass(); in hasLowDefLatency()
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600InstrInfo.cpp | 176 return (get(Opcode).getSchedClass() == AMDGPU::Sched::TransALU); in isTransOnly()
184 return (get(Opcode).getSchedClass() == AMDGPU::Sched::VecALU); in isVectorOnly()
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