| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 530 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 463 bool hasExtraDefRegAllocReq() const { in hasExtraDefRegAllocReq() function
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenInstruction.h | 243 bool hasExtraDefRegAllocReq; variable
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| D | InstrInfoEmitter.cpp | 297 if (Inst.hasExtraDefRegAllocReq) OS << "|(1<<MCID::ExtraDefRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 319 hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 252 bool hasExtraDefRegAllocReq : 1; variable
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| D | InstrInfoEmitter.cpp | 505 if (Inst.hasExtraDefRegAllocReq) OS << "|(1ULL<<MCID::ExtraDefRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 339 hasExtraDefRegAllocReq = R->getValueAsBit("hasExtraDefRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 248 let hasExtraDefRegAllocReq = 1 in
315 let hasExtraDefRegAllocReq = 1 in {
325 } // hasExtraDefRegAllocReq = 1
978 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
987 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1010 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1019 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| D | PPCInstrInfo.td | 2378 let hasExtraDefRegAllocReq = 1 in {
2388 } // hasExtraDefRegAllocReq = 1
2767 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2775 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2790 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2799 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| /external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 284 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
367 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
539 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
617 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
736 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
817 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430InstrInfo.td | 284 let mayLoad = 1, hasExtraDefRegAllocReq = 1, Constraints = "$base = $base_wb" in {
367 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
539 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
617 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
736 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
817 let mayLoad = 1, hasExtraDefRegAllocReq = 1,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 575 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || in BreakAntiDependencies()
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| D | AggressiveAntiDepBreaker.cpp | 387 if (MI->getDesc().isCall() || MI->getDesc().hasExtraDefRegAllocReq() || in PrescanInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 589 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
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| D | AggressiveAntiDepBreaker.cpp | 371 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 725 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 767 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
779 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
812 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
1530 hasExtraDefRegAllocReq = 1 in
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| D | ARMInstrInfo.td | 2534 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
2651 let hasExtraDefRegAllocReq = 1 in {
2679 } // hasExtraDefRegAllocReq = 1
3214 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3228 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
3235 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
4692 let hasExtraDefRegAllocReq = 1 in
4707 let hasExtraDefRegAllocReq = 1 in
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| D | ARMInstrThumb2.td | 1277 let mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1 in {
1282 } // mayLoad = 1, hasSideEffects = 0, hasExtraDefRegAllocReq = 1
1772 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3301 let hasExtraDefRegAllocReq = 1 in
3335 let hasExtraDefRegAllocReq = 1 in
3518 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 717 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
761 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
1413 hasExtraDefRegAllocReq = 1 in
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| D | ARMInstrInfo.td | 2191 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
2301 let hasExtraDefRegAllocReq = 1 in {
2330 } // hasExtraDefRegAllocReq = 1
2828 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
2839 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
4174 let hasExtraDefRegAllocReq = 1 in
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| D | ARMInstrThumb2.td | 1166 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1171 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1592 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
3011 let hasExtraDefRegAllocReq = 1 in
3109 hasExtraDefRegAllocReq = 1, isCodeGenOnly = 1 in
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| D | ARMInstrNEON.td | 214 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
539 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
623 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
876 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
905 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1084 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 528 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
|