| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInstrDesc.h | 520 bool hasExtraSrcRegAllocReq() const { in hasExtraSrcRegAllocReq() function
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrDesc.h | 453 bool hasExtraSrcRegAllocReq() const { in hasExtraSrcRegAllocReq() function
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| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| D | CodeGenInstruction.h | 242 bool hasExtraSrcRegAllocReq; variable
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| D | InstrInfoEmitter.cpp | 296 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1<<MCID::ExtraSrcRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 318 hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenInstruction.h | 251 bool hasExtraSrcRegAllocReq : 1; variable
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| D | InstrInfoEmitter.cpp | 504 if (Inst.hasExtraSrcRegAllocReq) OS << "|(1ULL<<MCID::ExtraSrcRegAllocReq)"; in emitRecord()
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| D | CodeGenInstruction.cpp | 338 hasExtraSrcRegAllocReq = R->getValueAsBit("hasExtraSrcRegAllocReq"); in CodeGenInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstr64Bit.td | 330 let hasExtraSrcRegAllocReq = 1 in {
340 } // hasExtraSrcRegAllocReq = 1
978 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
987 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1010 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
1019 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| D | PPCInstrInfo.td | 1599 let hasExtraSrcRegAllocReq = 1 in
2393 let hasExtraSrcRegAllocReq = 1 in {
2403 } // hasExtraSrcRegAllocReq = 1
2767 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2775 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2790 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
2799 let hasExtraSrcRegAllocReq = 1, hasExtraDefRegAllocReq = 1,
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| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 197 MI->getDesc().hasExtraSrcRegAllocReq() || in PrescanInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 455 MI->getDesc().hasExtraSrcRegAllocReq() || in ScanInstruction()
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| /external/llvm/lib/CodeGen/ |
| D | CriticalAntiDepBreaker.cpp | 167 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
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| D | AggressiveAntiDepBreaker.cpp | 448 bool Special = MI.isCall() || MI.hasExtraSrcRegAllocReq() || in ScanInstruction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstr.h | 715 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
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| /external/llvm/lib/Target/BPF/ |
| D | BPFInstrInfo.td | 528 hasExtraDefRegAllocReq = 1, hasExtraSrcRegAllocReq = 1, mayLoad = 1 in {
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 743 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
771 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
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| D | ARMInstrNEON.td | 1086 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1433 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1545 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1767 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
4853 let hasExtraSrcRegAllocReq = 1 in {
4867 } // hasExtraSrcRegAllocReq = 1
4883 let hasExtraSrcRegAllocReq = 1 in {
4899 } // hasExtraSrcRegAllocReq = 1
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| D | ARMInstrInfo.td | 2445 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
2605 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2636 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2831 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
4190 let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 794 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
822 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
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| D | ARMInstrInfo.td | 2808 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2973 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
3003 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
3218 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3239 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
4727 let hasExtraSrcRegAllocReq = 1 in
4745 let hasExtraSrcRegAllocReq = 1 in
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| D | ARMInstrNEON.td | 1609 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2023 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
2127 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in {
2349 } // mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1
6447 let hasExtraSrcRegAllocReq = 1 in {
6461 } // hasExtraSrcRegAllocReq = 1
6475 let hasExtraSrcRegAllocReq = 1 in {
6491 } // hasExtraSrcRegAllocReq = 1
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| D | ARMInstrThumb2.td | 1447 let mayStore = 1, hasSideEffects = 0, hasExtraSrcRegAllocReq = 1 in
1852 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
3382 let hasExtraSrcRegAllocReq = 1 in
3427 let hasExtraSrcRegAllocReq = 1 in
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| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 384 bit hasExtraSrcRegAllocReq = 1;
1354 hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT] in {
1931 let hasExtraSrcRegAllocReq = 1;
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| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| D | Target.td | 335 bit hasExtraSrcRegAllocReq = 0; // Sources have special regalloc requirement?
|