| /external/llvm/test/MC/AMDGPU/ |
| D | mubuf.s | 93 buffer_load_dword v1, v2, s[4:7], s1 idxen
97 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4
101 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc
105 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc
109 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe
113 buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe
117 buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe
121 buffer_load_dword v1, v2, ttmp[4:7], s1 idxen offset:4 glc slc tfe
129 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen
133 buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4
[all …]
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| /external/llvm/test/MC/Disassembler/AMDGPU/ |
| D | mubuf_vi.txt | 45 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen ; encoding: [0x00,0x20,0x50,0xe0,0x02,0x01,0x01,…
48 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 ; encoding: [0x04,0x20,0x50,0xe0,0x02,0…
51 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc ; encoding: [0x04,0x60,0x50,0xe0,0x…
54 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 slc ; encoding: [0x04,0x20,0x52,0xe0,0x…
57 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 tfe ; encoding: [0x04,0x20,0x50,0xe0,0x…
60 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen glc tfe ; encoding: [0x00,0x60,0x50,0xe0,0x02,0x…
63 # VI: buffer_load_dword v1, v2, s[4:7], s1 idxen offset:4 glc slc tfe ; encoding: [0x04,0x60,0x52…
66 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen ; encoding: [0x00,0x30,0x50,0xe0,0x02,…
69 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 ; encoding: [0x04,0x30,0x50,0…
72 # VI: buffer_load_dword v1, v[2:3], s[4:7], s1 idxen offen offset:4 glc ; encoding: [0x04,0x70,0x…
[all …]
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| /external/llvm/test/CodeGen/AMDGPU/ |
| D | llvm.amdgcn.buffer.atomic.ll | 8 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
12 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
35 ;CHECK: buffer_atomic_add v0, v1, s[0:3], 0 idxen glc
37 ;CHECK: buffer_atomic_sub v0, v1, s[0:3], 0 idxen glc
39 ;CHECK: buffer_atomic_smin v0, v1, s[0:3], 0 idxen glc
41 ;CHECK: buffer_atomic_umin v0, v1, s[0:3], 0 idxen glc
43 ;CHECK: buffer_atomic_smax v0, v1, s[0:3], 0 idxen glc
45 ;CHECK: buffer_atomic_umax v0, v1, s[0:3], 0 idxen glc
47 ;CHECK: buffer_atomic_and v0, v1, s[0:3], 0 idxen glc
49 ;CHECK: buffer_atomic_or v0, v1, s[0:3], 0 idxen glc
[all …]
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| D | llvm.amdgcn.buffer.store.ll | 25 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
41 ;CHECK: buffer_store_dwordx4 v[0:3], v[4:5], s[0:3], 0 idxen offen
50 ;CHECK: buffer_store_dwordx4 v[0:3], v[5:6], s[0:3], 0 idxen offen
60 ;CHECK: buffer_store_dwordx4 v[0:3], v4, s[0:3], 0 idxen
62 ;CHECK: buffer_load_dwordx4 v[0:3], v5, s[0:3], 0 idxen
64 ;CHECK: buffer_store_dwordx4 v[0:3], v6, s[0:3], 0 idxen
74 ;CHECK: buffer_store_dword v0, v1, s[0:3], 0 idxen
82 ;CHECK: buffer_store_dwordx2 v[0:1], v2, s[0:3], 0 idxen
|
| D | llvm.amdgcn.buffer.store.format.ll | 25 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
41 ;CHECK: buffer_store_format_xyzw v[0:3], v[4:5], s[0:3], 0 idxen offen
50 ;CHECK: buffer_store_format_xyzw v[0:3], v[5:6], s[0:3], 0 idxen offen
60 ;CHECK: buffer_store_format_xyzw v[0:3], v4, s[0:3], 0 idxen
62 ;CHECK: buffer_load_format_xyzw v[0:3], v5, s[0:3], 0 idxen
64 ;CHECK: buffer_store_format_xyzw v[0:3], v6, s[0:3], 0 idxen
74 ;CHECK: buffer_store_format_x v0, v1, s[0:3], 0 idxen
82 ;CHECK: buffer_store_format_xy v[0:1], v2, s[0:3], 0 idxen
|
| D | llvm.amdgcn.buffer.load.ll | 41 ;CHECK: buffer_load_dwordx4 v[0:3], v0, s[0:3], 0 idxen
69 ;CHECK: buffer_load_dwordx4 v[0:3], v[0:1], s[0:3], 0 idxen offen
79 ;CHECK: buffer_load_dwordx4 v[0:3], v[1:2], s[0:3], 0 idxen offen
88 ;CHECK: buffer_load_dword v0, v[0:1], s[0:3], 0 idxen offen
97 ;CHECK: buffer_load_dwordx2 v[0:1], v[0:1], s[0:3], 0 idxen offen
|
| D | llvm.SI.load.dword.ll | 12 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
13 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen off…
15 ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen…
|
| D | llvm.amdgcn.buffer.load.format.ll | 65 ;CHECK: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 idxen
93 ;CHECK: buffer_load_format_xyzw v[0:3], v[0:1], s[0:3], 0 idxen offen
103 ;CHECK: buffer_load_format_xyzw v[0:3], v[1:2], s[0:3], 0 idxen offen
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | VIInstrFormats.td | 37 bits<1> idxen;
49 let Inst{13} = idxen;
65 bits<1> idxen;
78 let Inst{13} = idxen;
|
| D | SIInstrInfo.td | 122 SDTCisVT<9, i32>, // idxen(imm)
538 def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
2857 (ins regClass:$vdata, u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
2860 opName#" $vdata, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2871 (ins u16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
2874 opName#" $dst, $offset, $offen, $idxen, $glc, $addr64, $dfmt,"
2916 bits<1> idxen;
2980 let offen = 0, idxen = 0, tfe = 0, vaddr = 0 in {
2996 let offen = 0, idxen = 0, addr64 = 1, tfe = 0 in {
3041 let offen = 1, idxen = 0 in {
[all …]
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| D | SIIntrinsics.td | 33 llvm_i32_ty, // idxen(imm)
47 llvm_i32_ty, // idxen(imm)
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| D | SIInstrFormats.td | 508 bits<1> idxen;
521 let Inst{13} = idxen;
539 bits<1> idxen;
552 let Inst{13} = idxen;
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| D | SIInstructions.td | 3221 multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen,
3244 (idxen $vaddr, $rsrc, $soffset, (as_i16imm $offset), (as_i1imm $glc),
3303 imm:$nfmt, imm:$offen, imm:$idxen,
3306 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen),
|
| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_shader.c | 824 unsigned idxen, in build_tbuffer_store() argument
840 LLVMConstInt(ctx->i32, idxen, 0), in build_tbuffer_store()
|