1//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// SI Instruction format definitions. 11// 12//===----------------------------------------------------------------------===// 13 14class InstSI <dag outs, dag ins, string asm = "", 15 list<dag> pattern = []> : 16 AMDGPUInst<outs, ins, asm, pattern>, PredicateControl { 17 18 field bits<1> VM_CNT = 0; 19 field bits<1> EXP_CNT = 0; 20 field bits<1> LGKM_CNT = 0; 21 22 field bits<1> SALU = 0; 23 field bits<1> VALU = 0; 24 25 field bits<1> SOP1 = 0; 26 field bits<1> SOP2 = 0; 27 field bits<1> SOPC = 0; 28 field bits<1> SOPK = 0; 29 field bits<1> SOPP = 0; 30 31 field bits<1> VOP1 = 0; 32 field bits<1> VOP2 = 0; 33 field bits<1> VOP3 = 0; 34 field bits<1> VOPC = 0; 35 field bits<1> SDWA = 0; 36 field bits<1> DPP = 0; 37 38 field bits<1> MUBUF = 0; 39 field bits<1> MTBUF = 0; 40 field bits<1> SMRD = 0; 41 field bits<1> DS = 0; 42 field bits<1> MIMG = 0; 43 field bits<1> FLAT = 0; 44 field bits<1> WQM = 0; 45 field bits<1> VGPRSpill = 0; 46 47 // This bit tells the assembler to use the 32-bit encoding in case it 48 // is unable to infer the encoding from the operands. 49 field bits<1> VOPAsmPrefer32Bit = 0; 50 51 field bits<1> Gather4 = 0; 52 53 // These need to be kept in sync with the enum in SIInstrFlags. 54 let TSFlags{0} = VM_CNT; 55 let TSFlags{1} = EXP_CNT; 56 let TSFlags{2} = LGKM_CNT; 57 58 let TSFlags{3} = SALU; 59 let TSFlags{4} = VALU; 60 61 let TSFlags{5} = SOP1; 62 let TSFlags{6} = SOP2; 63 let TSFlags{7} = SOPC; 64 let TSFlags{8} = SOPK; 65 let TSFlags{9} = SOPP; 66 67 let TSFlags{10} = VOP1; 68 let TSFlags{11} = VOP2; 69 let TSFlags{12} = VOP3; 70 let TSFlags{13} = VOPC; 71 let TSFlags{14} = SDWA; 72 let TSFlags{15} = DPP; 73 74 let TSFlags{16} = MUBUF; 75 let TSFlags{17} = MTBUF; 76 let TSFlags{18} = SMRD; 77 let TSFlags{19} = DS; 78 let TSFlags{20} = MIMG; 79 let TSFlags{21} = FLAT; 80 let TSFlags{22} = WQM; 81 let TSFlags{23} = VGPRSpill; 82 let TSFlags{24} = VOPAsmPrefer32Bit; 83 let TSFlags{25} = Gather4; 84 85 let SchedRW = [Write32Bit]; 86 87 field bits<1> DisableSIDecoder = 0; 88 field bits<1> DisableVIDecoder = 0; 89 field bits<1> DisableDecoder = 0; 90 91 let isAsmParserOnly = !if(!eq(DisableDecoder{0}, {0}), 0, 1); 92} 93 94class PseudoInstSI<dag outs, dag ins, list<dag> pattern = []> 95 : InstSI<outs, ins, "", pattern> { 96 let isPseudo = 1; 97 let isCodeGenOnly = 1; 98} 99 100class Enc32 { 101 field bits<32> Inst; 102 int Size = 4; 103} 104 105class Enc64 { 106 field bits<64> Inst; 107 int Size = 8; 108} 109 110class VOPDstOperand <RegisterClass rc> : RegisterOperand <rc, "printVOPDst">; 111 112let Uses = [EXEC] in { 113 114class VOPAnyCommon <dag outs, dag ins, string asm, list<dag> pattern> : 115 InstSI <outs, ins, asm, pattern> { 116 117 let mayLoad = 0; 118 let mayStore = 0; 119 let hasSideEffects = 0; 120 let UseNamedOperandTable = 1; 121 let VALU = 1; 122} 123 124class VOPCCommon <dag ins, string asm, list<dag> pattern> : 125 VOPAnyCommon <(outs), ins, asm, pattern> { 126 127 let VOPC = 1; 128 let Size = 4; 129 let Defs = [VCC]; 130} 131 132class VOP1Common <dag outs, dag ins, string asm, list<dag> pattern> : 133 VOPAnyCommon <outs, ins, asm, pattern> { 134 135 let VOP1 = 1; 136 let Size = 4; 137} 138 139class VOP2Common <dag outs, dag ins, string asm, list<dag> pattern> : 140 VOPAnyCommon <outs, ins, asm, pattern> { 141 142 let VOP2 = 1; 143 let Size = 4; 144} 145 146class VOP3Common <dag outs, dag ins, string asm = "", 147 list<dag> pattern = [], bit HasMods = 0, 148 bit VOP3Only = 0> : 149 VOPAnyCommon <outs, ins, asm, pattern> { 150 151 // Using complex patterns gives VOP3 patterns a very high complexity rating, 152 // but standalone patterns are almost always prefered, so we need to adjust the 153 // priority lower. The goal is to use a high number to reduce complexity to 154 // zero (or less than zero). 155 let AddedComplexity = -1000; 156 157 let VOP3 = 1; 158 let VALU = 1; 159 160 let AsmMatchConverter = 161 !if(!eq(VOP3Only,1), 162 "cvtVOP3", 163 !if(!eq(HasMods,1), "cvtVOP3_2_mod", "")); 164 165 let isCodeGenOnly = 0; 166 167 int Size = 8; 168 169 // Because SGPRs may be allowed if there are multiple operands, we 170 // need a post-isel hook to insert copies in order to avoid 171 // violating constant bus requirements. 172 let hasPostISelHook = 1; 173} 174 175} // End Uses = [EXEC] 176 177//===----------------------------------------------------------------------===// 178// Scalar operations 179//===----------------------------------------------------------------------===// 180 181class SOP1e <bits<8> op> : Enc32 { 182 bits<7> sdst; 183 bits<8> src0; 184 185 let Inst{7-0} = src0; 186 let Inst{15-8} = op; 187 let Inst{22-16} = sdst; 188 let Inst{31-23} = 0x17d; //encoding; 189} 190 191class SOP2e <bits<7> op> : Enc32 { 192 bits<7> sdst; 193 bits<8> src0; 194 bits<8> src1; 195 196 let Inst{7-0} = src0; 197 let Inst{15-8} = src1; 198 let Inst{22-16} = sdst; 199 let Inst{29-23} = op; 200 let Inst{31-30} = 0x2; // encoding 201} 202 203class SOPCe <bits<7> op> : Enc32 { 204 bits<8> src0; 205 bits<8> src1; 206 207 let Inst{7-0} = src0; 208 let Inst{15-8} = src1; 209 let Inst{22-16} = op; 210 let Inst{31-23} = 0x17e; 211} 212 213class SOPKe <bits<5> op> : Enc32 { 214 bits <7> sdst; 215 bits <16> simm16; 216 217 let Inst{15-0} = simm16; 218 let Inst{22-16} = sdst; 219 let Inst{27-23} = op; 220 let Inst{31-28} = 0xb; //encoding 221} 222 223class SOPK64e <bits<5> op> : Enc64 { 224 bits <7> sdst = 0; 225 bits <16> simm16; 226 bits <32> imm; 227 228 let Inst{15-0} = simm16; 229 let Inst{22-16} = sdst; 230 let Inst{27-23} = op; 231 let Inst{31-28} = 0xb; 232 233 let Inst{63-32} = imm; 234} 235 236class SOPPe <bits<7> op> : Enc32 { 237 bits <16> simm16; 238 239 let Inst{15-0} = simm16; 240 let Inst{22-16} = op; 241 let Inst{31-23} = 0x17f; // encoding 242} 243 244class SMRDe <bits<5> op, bits<1> imm> : Enc32 { 245 bits<7> sdst; 246 bits<7> sbase; 247 248 let Inst{8} = imm; 249 let Inst{14-9} = sbase{6-1}; 250 let Inst{21-15} = sdst; 251 let Inst{26-22} = op; 252 let Inst{31-27} = 0x18; //encoding 253} 254 255class SMRD_IMMe <bits<5> op> : SMRDe<op, 1> { 256 bits<8> offset; 257 let Inst{7-0} = offset; 258} 259 260class SMRD_SOFFe <bits<5> op> : SMRDe<op, 0> { 261 bits<8> soff; 262 let Inst{7-0} = soff; 263} 264 265 266 267class SMRD_IMMe_ci <bits<5> op> : Enc64 { 268 bits<7> sdst; 269 bits<7> sbase; 270 bits<32> offset; 271 272 let Inst{7-0} = 0xff; 273 let Inst{8} = 0; 274 let Inst{14-9} = sbase{6-1}; 275 let Inst{21-15} = sdst; 276 let Inst{26-22} = op; 277 let Inst{31-27} = 0x18; //encoding 278 let Inst{63-32} = offset; 279} 280 281let SchedRW = [WriteSALU] in { 282class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> : 283 InstSI<outs, ins, asm, pattern> { 284 let mayLoad = 0; 285 let mayStore = 0; 286 let hasSideEffects = 0; 287 let isCodeGenOnly = 0; 288 let SALU = 1; 289 let SOP1 = 1; 290} 291 292class SOP2 <dag outs, dag ins, string asm, list<dag> pattern> : 293 InstSI <outs, ins, asm, pattern> { 294 295 let mayLoad = 0; 296 let mayStore = 0; 297 let hasSideEffects = 0; 298 let isCodeGenOnly = 0; 299 let SALU = 1; 300 let SOP2 = 1; 301 302 let UseNamedOperandTable = 1; 303} 304 305class SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 306 InstSI<outs, ins, asm, pattern>, SOPCe <op> { 307 308 let mayLoad = 0; 309 let mayStore = 0; 310 let hasSideEffects = 0; 311 let SALU = 1; 312 let SOPC = 1; 313 let isCodeGenOnly = 0; 314 let Defs = [SCC]; 315 316 let UseNamedOperandTable = 1; 317} 318 319class SOPK <dag outs, dag ins, string asm, list<dag> pattern> : 320 InstSI <outs, ins , asm, pattern> { 321 322 let mayLoad = 0; 323 let mayStore = 0; 324 let hasSideEffects = 0; 325 let SALU = 1; 326 let SOPK = 1; 327 328 let UseNamedOperandTable = 1; 329} 330 331class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> : 332 InstSI <(outs), ins, asm, pattern >, SOPPe <op> { 333 334 let mayLoad = 0; 335 let mayStore = 0; 336 let hasSideEffects = 0; 337 let SALU = 1; 338 let SOPP = 1; 339 340 let UseNamedOperandTable = 1; 341} 342 343} // let SchedRW = [WriteSALU] 344 345class SMRD <dag outs, dag ins, string asm, list<dag> pattern> : 346 InstSI<outs, ins, asm, pattern> { 347 348 let LGKM_CNT = 1; 349 let SMRD = 1; 350 let mayStore = 0; 351 let mayLoad = 1; 352 let hasSideEffects = 0; 353 let UseNamedOperandTable = 1; 354 let SchedRW = [WriteSMEM]; 355} 356 357//===----------------------------------------------------------------------===// 358// Vector ALU operations 359//===----------------------------------------------------------------------===// 360 361class VOP1e <bits<8> op> : Enc32 { 362 bits<8> vdst; 363 bits<9> src0; 364 365 let Inst{8-0} = src0; 366 let Inst{16-9} = op; 367 let Inst{24-17} = vdst; 368 let Inst{31-25} = 0x3f; //encoding 369} 370 371class VOP2e <bits<6> op> : Enc32 { 372 bits<8> vdst; 373 bits<9> src0; 374 bits<8> src1; 375 376 let Inst{8-0} = src0; 377 let Inst{16-9} = src1; 378 let Inst{24-17} = vdst; 379 let Inst{30-25} = op; 380 let Inst{31} = 0x0; //encoding 381} 382 383class VOP2_MADKe <bits<6> op> : Enc64 { 384 385 bits<8> vdst; 386 bits<9> src0; 387 bits<8> src1; 388 bits<32> imm; 389 390 let Inst{8-0} = src0; 391 let Inst{16-9} = src1; 392 let Inst{24-17} = vdst; 393 let Inst{30-25} = op; 394 let Inst{31} = 0x0; // encoding 395 let Inst{63-32} = imm; 396} 397 398class VOP3a <bits<9> op> : Enc64 { 399 bits<2> src0_modifiers; 400 bits<9> src0; 401 bits<2> src1_modifiers; 402 bits<9> src1; 403 bits<2> src2_modifiers; 404 bits<9> src2; 405 bits<1> clamp; 406 bits<2> omod; 407 408 let Inst{8} = src0_modifiers{1}; 409 let Inst{9} = src1_modifiers{1}; 410 let Inst{10} = src2_modifiers{1}; 411 let Inst{11} = clamp; 412 let Inst{25-17} = op; 413 let Inst{31-26} = 0x34; //encoding 414 let Inst{40-32} = src0; 415 let Inst{49-41} = src1; 416 let Inst{58-50} = src2; 417 let Inst{60-59} = omod; 418 let Inst{61} = src0_modifiers{0}; 419 let Inst{62} = src1_modifiers{0}; 420 let Inst{63} = src2_modifiers{0}; 421} 422 423class VOP3e <bits<9> op> : VOP3a <op> { 424 bits<8> vdst; 425 426 let Inst{7-0} = vdst; 427} 428 429// Encoding used for VOPC instructions encoded as VOP3 430// Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst 431class VOP3ce <bits<9> op> : VOP3a <op> { 432 bits<8> sdst; 433 434 let Inst{7-0} = sdst; 435} 436 437class VOP3be <bits<9> op> : Enc64 { 438 bits<8> vdst; 439 bits<2> src0_modifiers; 440 bits<9> src0; 441 bits<2> src1_modifiers; 442 bits<9> src1; 443 bits<2> src2_modifiers; 444 bits<9> src2; 445 bits<7> sdst; 446 bits<2> omod; 447 448 let Inst{7-0} = vdst; 449 let Inst{14-8} = sdst; 450 let Inst{25-17} = op; 451 let Inst{31-26} = 0x34; //encoding 452 let Inst{40-32} = src0; 453 let Inst{49-41} = src1; 454 let Inst{58-50} = src2; 455 let Inst{60-59} = omod; 456 let Inst{61} = src0_modifiers{0}; 457 let Inst{62} = src1_modifiers{0}; 458 let Inst{63} = src2_modifiers{0}; 459} 460 461class VOPCe <bits<8> op> : Enc32 { 462 bits<9> src0; 463 bits<8> src1; 464 465 let Inst{8-0} = src0; 466 let Inst{16-9} = src1; 467 let Inst{24-17} = op; 468 let Inst{31-25} = 0x3e; 469} 470 471class VINTRPe <bits<2> op> : Enc32 { 472 bits<8> vdst; 473 bits<8> vsrc; 474 bits<2> attrchan; 475 bits<6> attr; 476 477 let Inst{7-0} = vsrc; 478 let Inst{9-8} = attrchan; 479 let Inst{15-10} = attr; 480 let Inst{17-16} = op; 481 let Inst{25-18} = vdst; 482 let Inst{31-26} = 0x32; // encoding 483} 484 485class DSe <bits<8> op> : Enc64 { 486 bits<8> vdst; 487 bits<1> gds; 488 bits<8> addr; 489 bits<8> data0; 490 bits<8> data1; 491 bits<8> offset0; 492 bits<8> offset1; 493 494 let Inst{7-0} = offset0; 495 let Inst{15-8} = offset1; 496 let Inst{17} = gds; 497 let Inst{25-18} = op; 498 let Inst{31-26} = 0x36; //encoding 499 let Inst{39-32} = addr; 500 let Inst{47-40} = data0; 501 let Inst{55-48} = data1; 502 let Inst{63-56} = vdst; 503} 504 505class MUBUFe <bits<7> op> : Enc64 { 506 bits<12> offset; 507 bits<1> offen; 508 bits<1> idxen; 509 bits<1> glc; 510 bits<1> addr64; 511 bits<1> lds; 512 bits<8> vaddr; 513 bits<8> vdata; 514 bits<7> srsrc; 515 bits<1> slc; 516 bits<1> tfe; 517 bits<8> soffset; 518 519 let Inst{11-0} = offset; 520 let Inst{12} = offen; 521 let Inst{13} = idxen; 522 let Inst{14} = glc; 523 let Inst{15} = addr64; 524 let Inst{16} = lds; 525 let Inst{24-18} = op; 526 let Inst{31-26} = 0x38; //encoding 527 let Inst{39-32} = vaddr; 528 let Inst{47-40} = vdata; 529 let Inst{52-48} = srsrc{6-2}; 530 let Inst{54} = slc; 531 let Inst{55} = tfe; 532 let Inst{63-56} = soffset; 533} 534 535class MTBUFe <bits<3> op> : Enc64 { 536 bits<8> vdata; 537 bits<12> offset; 538 bits<1> offen; 539 bits<1> idxen; 540 bits<1> glc; 541 bits<1> addr64; 542 bits<4> dfmt; 543 bits<3> nfmt; 544 bits<8> vaddr; 545 bits<7> srsrc; 546 bits<1> slc; 547 bits<1> tfe; 548 bits<8> soffset; 549 550 let Inst{11-0} = offset; 551 let Inst{12} = offen; 552 let Inst{13} = idxen; 553 let Inst{14} = glc; 554 let Inst{15} = addr64; 555 let Inst{18-16} = op; 556 let Inst{22-19} = dfmt; 557 let Inst{25-23} = nfmt; 558 let Inst{31-26} = 0x3a; //encoding 559 let Inst{39-32} = vaddr; 560 let Inst{47-40} = vdata; 561 let Inst{52-48} = srsrc{6-2}; 562 let Inst{54} = slc; 563 let Inst{55} = tfe; 564 let Inst{63-56} = soffset; 565} 566 567class MIMGe <bits<7> op> : Enc64 { 568 bits<8> vdata; 569 bits<4> dmask; 570 bits<1> unorm; 571 bits<1> glc; 572 bits<1> da; 573 bits<1> r128; 574 bits<1> tfe; 575 bits<1> lwe; 576 bits<1> slc; 577 bits<8> vaddr; 578 bits<7> srsrc; 579 bits<7> ssamp; 580 581 let Inst{11-8} = dmask; 582 let Inst{12} = unorm; 583 let Inst{13} = glc; 584 let Inst{14} = da; 585 let Inst{15} = r128; 586 let Inst{16} = tfe; 587 let Inst{17} = lwe; 588 let Inst{24-18} = op; 589 let Inst{25} = slc; 590 let Inst{31-26} = 0x3c; 591 let Inst{39-32} = vaddr; 592 let Inst{47-40} = vdata; 593 let Inst{52-48} = srsrc{6-2}; 594 let Inst{57-53} = ssamp{6-2}; 595} 596 597class FLATe<bits<7> op> : Enc64 { 598 bits<8> addr; 599 bits<8> data; 600 bits<8> vdst; 601 bits<1> slc; 602 bits<1> glc; 603 bits<1> tfe; 604 605 // 15-0 is reserved. 606 let Inst{16} = glc; 607 let Inst{17} = slc; 608 let Inst{24-18} = op; 609 let Inst{31-26} = 0x37; // Encoding. 610 let Inst{39-32} = addr; 611 let Inst{47-40} = data; 612 // 54-48 is reserved. 613 let Inst{55} = tfe; 614 let Inst{63-56} = vdst; 615} 616 617class EXPe : Enc64 { 618 bits<4> en; 619 bits<6> tgt; 620 bits<1> compr; 621 bits<1> done; 622 bits<1> vm; 623 bits<8> vsrc0; 624 bits<8> vsrc1; 625 bits<8> vsrc2; 626 bits<8> vsrc3; 627 628 let Inst{3-0} = en; 629 let Inst{9-4} = tgt; 630 let Inst{10} = compr; 631 let Inst{11} = done; 632 let Inst{12} = vm; 633 let Inst{31-26} = 0x3e; 634 let Inst{39-32} = vsrc0; 635 let Inst{47-40} = vsrc1; 636 let Inst{55-48} = vsrc2; 637 let Inst{63-56} = vsrc3; 638} 639 640let Uses = [EXEC] in { 641 642class VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 643 VOP1Common <outs, ins, asm, pattern>, 644 VOP1e<op> { 645 let isCodeGenOnly = 0; 646} 647 648class VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 649 VOP2Common <outs, ins, asm, pattern>, VOP2e<op> { 650 let isCodeGenOnly = 0; 651} 652 653class VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 654 VOPCCommon <ins, asm, pattern>, VOPCe <op>; 655 656class VINTRPCommon <dag outs, dag ins, string asm, list<dag> pattern> : 657 InstSI <outs, ins, asm, pattern> { 658 let mayLoad = 1; 659 let mayStore = 0; 660 let hasSideEffects = 0; 661} 662 663} // End Uses = [EXEC] 664 665//===----------------------------------------------------------------------===// 666// Vector I/O operations 667//===----------------------------------------------------------------------===// 668 669class DS <dag outs, dag ins, string asm, list<dag> pattern> : 670 InstSI <outs, ins, asm, pattern> { 671 672 let LGKM_CNT = 1; 673 let DS = 1; 674 let UseNamedOperandTable = 1; 675 let Uses = [M0, EXEC]; 676 677 // Most instruction load and store data, so set this as the default. 678 let mayLoad = 1; 679 let mayStore = 1; 680 681 let hasSideEffects = 0; 682 let AsmMatchConverter = "cvtDS"; 683 let SchedRW = [WriteLDS]; 684} 685 686class MUBUF <dag outs, dag ins, string asm, list<dag> pattern> : 687 InstSI<outs, ins, asm, pattern> { 688 689 let VM_CNT = 1; 690 let EXP_CNT = 1; 691 let MUBUF = 1; 692 let Uses = [EXEC]; 693 694 let hasSideEffects = 0; 695 let UseNamedOperandTable = 1; 696 let AsmMatchConverter = "cvtMubuf"; 697 let SchedRW = [WriteVMEM]; 698} 699 700class MTBUF <dag outs, dag ins, string asm, list<dag> pattern> : 701 InstSI<outs, ins, asm, pattern> { 702 703 let VM_CNT = 1; 704 let EXP_CNT = 1; 705 let MTBUF = 1; 706 let Uses = [EXEC]; 707 708 let hasSideEffects = 0; 709 let UseNamedOperandTable = 1; 710 let SchedRW = [WriteVMEM]; 711} 712 713class FLAT <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 714 InstSI<outs, ins, asm, pattern>, FLATe <op> { 715 let FLAT = 1; 716 // Internally, FLAT instruction are executed as both an LDS and a 717 // Buffer instruction; so, they increment both VM_CNT and LGKM_CNT 718 // and are not considered done until both have been decremented. 719 let VM_CNT = 1; 720 let LGKM_CNT = 1; 721 722 let Uses = [EXEC, FLAT_SCR]; // M0 723 724 let UseNamedOperandTable = 1; 725 let hasSideEffects = 0; 726 let SchedRW = [WriteVMEM]; 727} 728 729class MIMG <dag outs, dag ins, string asm, list<dag> pattern> : 730 InstSI <outs, ins, asm, pattern> { 731 732 let VM_CNT = 1; 733 let EXP_CNT = 1; 734 let MIMG = 1; 735 let Uses = [EXEC]; 736 737 let UseNamedOperandTable = 1; 738 let hasSideEffects = 0; // XXX ???? 739} 740