| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86GenFastISel.inc | 4091 unsigned FastEmit_ISD_ADD_MVT_i8_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4094 return FastEmitInst_ri(X86::ADD8ri, X86::GR8RegisterClass, Op0, Op0IsKill, imm1);
4097 unsigned FastEmit_ISD_ADD_MVT_i16_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4100 return FastEmitInst_ri(X86::ADD16ri, X86::GR16RegisterClass, Op0, Op0IsKill, imm1);
4103 unsigned FastEmit_ISD_ADD_MVT_i32_ri(MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4106 return FastEmitInst_ri(X86::ADD32ri, X86::GR32RegisterClass, Op0, Op0IsKill, imm1);
4109 unsigned FastEmit_ISD_ADD_ri(MVT VT, MVT RetVT, unsigned Op0, bool Op0IsKill, uint64_t imm1) {
4111 case MVT::i8: return FastEmit_ISD_ADD_MVT_i8_ri(RetVT, Op0, Op0IsKill, imm1);
4112 case MVT::i16: return FastEmit_ISD_ADD_MVT_i16_ri(RetVT, Op0, Op0IsKill, imm1);
4113 case MVT::i32: return FastEmit_ISD_ADD_MVT_i32_ri(RetVT, Op0, Op0IsKill, imm1);
[all …]
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| D | README-SSE.txt | 502 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/mesa3d/src/compiler/glsl/ |
| D | lower_blend_equation_advanced.cpp | 34 #define imm1(x) new(mem_ctx) ir_constant((float) (x), 1) macro
227 f->emit(if_tree(less(mincol, imm1(0)), in set_lum()
230 if_tree(greater(maxcol, imm1(1)), in set_lum()
261 f->emit(if_tree(greater(sbase, imm1(0)), in set_lum_sat()
309 f.emit(if_tree(equal(dst_alpha, imm1(0)), in calc_blend_result()
317 f.emit(if_tree(equal(src_alpha, imm1(0)), in calc_blend_result()
405 f.emit(assign(p1, mul(src_alpha, sub(imm1(1), dst_alpha)))); in calc_blend_result()
406 f.emit(assign(p2, mul(dst_alpha, sub(imm1(1), src_alpha)))); in calc_blend_result()
|
| /external/mesa3d/src/gallium/drivers/nouveau/codegen/ |
| D | nv50_ir_peephole.cpp | 518 ImmediateValue &imm0, ImmediateValue &imm1) in expr() argument
520 struct Storage *const a = &imm0.reg, *const b = &imm1.reg; in expr()
737 ImmediateValue &imm1, in expr() argument
740 struct Storage *const a = &imm0.reg, *const b = &imm1.reg, *const c = &imm2.reg; in expr()
844 ImmediateValue imm1; in tryCollapseChainedMULs() local
855 if (mul1->src(s1 = 0).getImmediate(imm1) || in tryCollapseChainedMULs()
856 mul1->src(s1 = 1).getImmediate(imm1)) { in tryCollapseChainedMULs()
860 mul1->setSrc(s1, bld.loadImm(NULL, f * imm1.reg.data.f32)); in tryCollapseChainedMULs()
889 if (!insn->src(s2).mod && !insn->src(t2).getImmediate(imm1)) in tryCollapseChainedMULs()
1217 ImmediateValue imm1; in opnd() local
[all …]
|
| /external/v8/src/wasm/ |
| D | wasm-module-builder.cc | 120 void WasmFunctionBuilder::EmitWithU8U8(WasmOpcode opcode, const byte imm1, in EmitWithU8U8() argument
123 body_.push_back(imm1); in EmitWithU8U8()
|
| D | wasm-module-builder.h | 133 void EmitWithU8U8(WasmOpcode opcode, const byte imm1, const byte imm2);
|
| /external/pcre/dist2/src/sljit/ |
| D | sljitNativeARM_32.c | 1181 sljit_uw imm1; in generate_int() local
1224 imm1 = SRC2_IMM | ((imm >> 16) & 0xff) | (((rol + 4) & 0xf) << 8); in generate_int()
1228 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1263 imm1 = SRC2_IMM | ((imm >> 24) & 0xff) | ((rol & 0xf) << 8); in generate_int()
1283 …ush_inst(compiler, EMIT_DATA_PROCESS_INS(positive ? MOV_DP : MVN_DP, 0, reg, SLJIT_UNUSED, imm1))); in generate_int()
|
| /external/vixl/test/aarch64/ |
| D | test-simulator-aarch64.cc | 172 const VRegister& vd, int imm1, const VRegister& vn, int imm2);
2592 for (unsigned imm1 = 0; imm1 < inputs_imm1_length; imm1++) { in TestOpImmOpImmNEON() local
2601 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2628 (imm1 * inputs_imm2_length * vd_lane_count) + in TestOpImmOpImmNEON()
2633 unsigned input_index_imm1 = imm1; in TestOpImmOpImmNEON()
|
| /external/llvm/lib/Target/X86/ |
| D | README-SSE.txt | 467 INSERTPS can match any insert (extract, imm1), imm2 for 4 x float, and insert
|
| /external/valgrind/VEX/priv/ |
| D | host_ppc_defs.c | 3298 UInt imm1, UInt imm2, UInt opc2, in mkFormMD() argument
3305 vassert(imm1 < 0x40); in mkFormMD()
3310 ((imm1 & 0x1F)<<11) | (imm2<<5) | in mkFormMD()
3311 (opc2<<2) | ((imm1 >> 5)<<1)); in mkFormMD()
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| D | guest_arm_toIR.c | 2596 UInt imm1, UInt imm3, UInt imm8 ) in thumbExpandImm() argument
2598 vassert(imm1 < (1<<1)); in thumbExpandImm()
2601 UInt i_imm3_a = (imm1 << 4) | (imm3 << 1) | ((imm8 >> 7) & 1); in thumbExpandImm()
2633 UInt imm1 = SLICE_UInt(i0,10,10); in thumbExpandImm_from_I0_I1() local
2636 return thumbExpandImm(updatesC, imm1, imm3, imm8); in thumbExpandImm_from_I0_I1()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsFastISel.cpp | 187 unsigned Op0, bool Op0IsKill, uint64_t imm1, in fastEmitInst_riir() argument
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXIntrinsics.td | 80 def imm1 : NVPTXInst<
954 def imm1 : NVPTXInst<(outs regclass:$dst),
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| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 4320 // SETPAN #imm1
|
| D | ARMInstrInfo.td | 4338 // SETPAN #imm1
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrFormats.td | 635 // {0} - imm1: #8 or #16
|