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Searched refs:imm12 (Results 1 – 23 of 23) sorted by relevance

/external/vixl/test/aarch32/config/
Dcond-rd-rn-operand-imm12-t32.json28 // MNEMONIC{<c>}.W <Rd>, <Rn>, #<imm12>
29 // MNEMONIC{<c>}.W <Rd>, SP, #<imm12>
33 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
34 // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
35 "Addw", // ADDW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
36 // ADDW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4
37 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
38 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
39 "Subw" // SUBW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4
40 // SUBW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3
[all …]
Dcond-rd-pc-operand-imm12-t32.json28 // MNEMONIC{<c>}.W <Rd>, PC, #<imm12>
32 "Add", // ADD{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
33 "Addw", // ADDW{<c>}{<q>} <Rd>, PC, #<imm12> ; T3
34 "Sub" // SUB{<c>}{<q>} <Rd>, PC, #<imm12> ; T2
/external/llvm/test/CodeGen/AArch64/
Darm64-addrmode.ll28 ; base + unsigned offset (> imm9 and <= imm12 * size of type in bytes)
38 ; base + unsigned offset (> imm12 * size of type in bytes)
/external/v8/src/arm64/
Dassembler-arm64-inl.h1109 Instr Assembler::ImmLSUnsigned(int imm12) {
1110 DCHECK(is_uint12(imm12));
1111 return imm12 << ImmLSUnsigned_offset;
Dassembler-arm64.h1786 inline static Instr ImmLSUnsigned(int imm12);
/external/valgrind/VEX/priv/
Dhost_arm64_defs.h164 UShort imm12; /* 0 .. 4095 */ member
174 extern ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift );
Dguest_arm_toIR.c2396 IRExpr* mk_EA_reg_plusminus_imm12 ( UInt rN, UInt bU, UInt imm12, in mk_EA_reg_plusminus_imm12() argument
2401 vassert(imm12 < 0x1000); in mk_EA_reg_plusminus_imm12()
2403 DIS(buf, "[r%u, #%c%u]", rN, opChar, imm12); in mk_EA_reg_plusminus_imm12()
2407 mkU32(imm12) ); in mk_EA_reg_plusminus_imm12()
15940 UInt imm12 = INSN(11,0); in decode_NV_instruction_ARMv7_and_below() local
15943 DIP("pld%c [r%u, #%c%u]\n", bR ? ' ' : 'w', rN, bU ? '+' : '-', imm12); in decode_NV_instruction_ARMv7_and_below()
15975 UInt imm12 = INSN(11,0); in decode_NV_instruction_ARMv7_and_below() local
15977 DIP("pli [r%u, #%c%u]\n", rN, bU ? '+' : '-', imm12); in decode_NV_instruction_ARMv7_and_below()
16579 UInt imm12 = (insn >> 0) & 0xFFF; /* 11:0 */ in disInstr_ARM_WRK() local
16611 eaE = mk_EA_reg_plusminus_imm12( rN, bU, imm12, dis_buf ); in disInstr_ARM_WRK()
[all …]
Dhost_arm64_defs.c305 ARM64RIA* ARM64RIA_I12 ( UShort imm12, UChar shift ) { in ARM64RIA_I12() argument
308 riA->ARM64riA.I12.imm12 = imm12; in ARM64RIA_I12()
310 vassert(imm12 < 4096); in ARM64RIA_I12()
324 vex_printf("#%u",(UInt)(riA->ARM64riA.I12.imm12 in ppARM64RIA()
3307 argR->ARM64riA.I12.imm12, rN, rD in emit_ARM64Instr()
3335 argR->ARM64riA.I12.imm12, rN, rD); in emit_ARM64Instr()
Dguest_arm64_toIR.c5181 UInt imm12 = INSN(21,10); in dis_ARM64_load_store() local
5186 getIReg64orSP(nn), mkU64(imm12 * szB)); in dis_ARM64_load_store()
5192 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
5202 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
5212 nameIReg64orSP(nn), imm12 * szB); in dis_ARM64_load_store()
6658 UInt imm12 = INSN(21,10); in dis_ARM64_load_store() local
6664 assign(ea, binop(Iop_Add64, getIReg64orSP(nn), mkU64(imm12 * 8))); in dis_ARM64_load_store()
6665 DIP("prfm prfop=%u, [%s, #%u]\n", tt, nameIReg64orSP(nn), imm12 * 8); in dis_ARM64_load_store()
Dhost_arm64_isel.c923 vassert(ri->ARM64riA.I12.imm12 < 4096); in iselIntExpr_RIA()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td609 // addrmode_imm12 := reg +/- imm12
677 // addrmode2 := reg +/- imm12
1416 let Inst{11-0} = addr{11-0}; // imm12
1446 let Inst{11-0} = addr{11-0}; // imm12
1477 let Inst{11-0} = addr{11-0}; // imm12
1506 let Inst{11-0} = addr{11-0}; // imm12
1688 let Inst{11-0} = addr{11-0}; // imm12
2174 let Inst{11-0} = addr{11-0}; // imm12
2232 // {11-0} imm12/Rm
2249 // {11-0} imm12/Rm
[all …]
DARMInstrFormats.td545 // {11-0} imm12/Rm
563 // {11-0} imm12/Rm
582 // {13} 1 == Rm, 0 == imm12
584 // {11-0} imm12/Rm
DREADME.txt510 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
DARMInstrThumb2.td115 // t2addrmode_imm12 := reg + imm12
126 // t2ldrlabel := imm12
873 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
952 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1477 let Inst{11-0} = addr{11-0}; // imm12
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td815 // addrmode_imm12 := reg +/- imm12
891 // addrmode2 := reg +/- imm12
1738 let Inst{11-0} = addr{11-0}; // imm12
1769 let Inst{11-0} = addr{11-0}; // imm12
1801 let Inst{11-0} = addr{11-0}; // imm12
1830 let Inst{11-0} = addr{11-0}; // imm12
2006 let Inst{11-0} = addr{11-0}; // imm12
2517 let Inst{11-0} = addr{11-0}; // imm12
2580 // {11-0} imm12/Rm
2598 // {11-0} imm12/Rm
[all …]
DARMInstrFormats.td674 // {11-0} imm12/Rm
692 // {11-0} imm12/Rm
711 // {13} 1 == Rm, 0 == imm12
713 // {11-0} imm12/Rm
DARMInstrThumb2.td151 // t2addrmode_imm12 := reg + imm12
162 // t2ldrlabel := imm12
973 /// T2I_ld - Defines a set of (op r, {imm12|imm8|so_reg}) load patterns.
1061 /// T2I_st - Defines a set of (op r, {imm12|imm8|so_reg}) store patterns.
1629 let Inst{11-0} = addr{11-0}; // imm12
1694 let Inst{11-0} = addr{11-0}; // imm12
DREADME.txt505 LDR into imm12 and so_reg forms. This allows us to clean up some code. e.g.
/external/vixl/src/aarch64/
Dassembler-aarch64.h2774 static Instr ImmLSUnsigned(int64_t imm12) { in ImmLSUnsigned() argument
2775 VIXL_ASSERT(IsUint12(imm12)); in ImmLSUnsigned()
2776 return TruncateToUint12(imm12) << ImmLSUnsigned_offset; in ImmLSUnsigned()
/external/swiftshader/third_party/subzero/src/
DIceAssemblerARM32.h655 bool SetFlags, IValueT Rn, IValueT Rd, IValueT imm12,
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.td173 // FIXME: Provide imm12 variant
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp194 ADD imm12
235 SUB imm12
/external/valgrind/none/tests/arm/
Dv6intARM.stdout.exp779 pld reg +/- imm12 cases