1// Copyright 2016, VIXL authors 2// All rights reserved. 3// 4// Redistribution and use in source and binary forms, with or without 5// modification, are permitted provided that the following conditions are met: 6// 7// * Redistributions of source code must retain the above copyright notice, 8// this list of conditions and the following disclaimer. 9// * Redistributions in binary form must reproduce the above copyright notice, 10// this list of conditions and the following disclaimer in the documentation 11// and/or other materials provided with the distribution. 12// * Neither the name of ARM Limited nor the names of its contributors may be 13// used to endorse or promote products derived from this software without 14// specific prior written permission. 15// 16// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27// Test description for instructions of the following forms: 28// MNEMONIC{<c>}.W <Rd>, <Rn>, #<imm12> 29// MNEMONIC{<c>}.W <Rd>, SP, #<imm12> 30 31{ 32 "mnemonics" : [ 33 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 34 // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4 35 "Addw", // ADDW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 36 // ADDW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4 37 "Sub", // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 38 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3 39 "Subw" // SUBW{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 40 // SUBW{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3 41 ], 42 "description" : { 43 "operands": [ 44 { 45 "name": "cond", 46 "type": "Always" 47 }, 48 { 49 "name": "rd", 50 "type": "AllRegistersButPC" 51 }, 52 { 53 "name": "rn", 54 "type": "AllRegistersButPC" 55 }, 56 { 57 "name": "op", 58 "wrapper": "Operand", 59 "operands": [ 60 { 61 "name": "immediate", 62 "type": "OffsetLowerThan4096" 63 } 64 ] 65 } 66 ], 67 "inputs":[ 68 { 69 "name": "rd", 70 "type": "Register" 71 }, 72 { 73 "name": "rn", 74 "type": "Register" 75 } 76 ] 77 }, 78 "test-files": [ 79 { 80 "type": "assembler", 81 "test-cases": [ 82 { 83 "name": "Operands", 84 "operands": [ 85 "rd", "rn", "immediate" 86 ], 87 "operand-limit": 1000 88 } 89 ] 90 }, 91 { 92 "type": "simulator", 93 "mnemonics" : [ 94 "Add", // ADD{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 95 // ADD{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T4 96 "Sub" // SUB{<c>}{<q>} {<Rd>}, <Rn>, #<imm12> ; T4 97 // SUB{<c>}{<q>} {<Rd>}, SP, #<imm12> ; T3 98 ], 99 "test-cases": [ 100 { 101 "name": "RdIsRn", 102 "operands": [ 103 "rd", "rn", "immediate" 104 ], 105 "inputs": [ 106 "rd", "rn" 107 ], 108 "operand-filter": "rd == rn", 109 "operand-limit": 10, 110 "input-filter": "rd == rn" 111 }, 112 { 113 "name": "RdIsNotRn", 114 "operands": [ 115 "rd", "rn", "immediate" 116 ], 117 "inputs": [ 118 "rd", "rn" 119 ], 120 "operand-filter": "rd != rn", 121 "operand-limit": 10 122 }, 123 { 124 "name": "Immediate", 125 "operands": [ 126 "immediate" 127 ], 128 "operand-limit": 20, 129 "inputs": [ 130 "rn" 131 ] 132 } 133 ] 134 } 135 ] 136} 137