/external/vixl/test/aarch32/config/ |
D | cond-rd-operand-imm16-t32.json | 28 // MNEMONIC{<c>}.W <Rd>, #<imm16> 32 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3 33 "Movt", // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1 34 "Movw" // MOVW{<c>}{<q>} <Rd>, #<imm16> ; T3 84 "Mov", // MOV{<c>}{<q>} <Rd>, #<imm16> ; T3 85 "Movt" // MOVT{<c>}{<q>} <Rd>, #<imm16> ; T1
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/external/valgrind/none/tests/x86/ |
D | insn_basic.def | 35 adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] 36 adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] 37 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] 38 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] 39 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] 40 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] 68 addw imm16[1234] ax.uw[5678] => 1.uw[6912] 69 addw imm16[1234] bx.uw[5678] => 1.uw[6912] 70 addw imm16[1234] m16.uw[5678] => 1.uw[6912] 88 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230] [all …]
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrFormats.td | 436 bits<16> imm16; 441 let Inst{26-21} = imm16{10-5}; 442 let Inst{20-16} = imm16{15-11}; 445 let Inst{4-0} = imm16{4-0}; 487 bits<16> imm16; 493 let Inst{26-21} = imm16{10-5}; 494 let Inst{20-16} = imm16{15-11}; 498 let Inst{4-0} = imm16{4-0}; 512 bits<16> imm16; 518 let Inst{26-21} = imm16{10-5}; [all …]
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D | MipsInstrFormats.td | 177 bits<16> imm16; 183 let Inst{15-0} = imm16; 192 bits<16> imm16; 198 let Inst{15-0} = imm16; 236 bits<16> imm16; 243 let Inst{15-0} = imm16; 264 bits<16> imm16; 271 let Inst{15-0} = imm16; 347 bits<16> imm16; 354 let Inst{15-0} = imm16; [all …]
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D | Mips16InstrInfo.td | 55 FI16<op, (outs), (ins brtarget:$imm16), 56 !strconcat(asmstr, "\t$imm16 # 16 bit inst"), [], itin>; 152 FEXT_I16<eop, (outs), (ins brtarget:$imm16), 153 !strconcat(asmstr, "\t$imm16"),[], itin>; 1356 Mips16Pat<(OpNode bb:$imm16), (I bb:$imm16)> { 1394 Mips16Pat<(cond_op CPU16Regs:$rx, imm_type:$imm16), 1395 (I CPU16Regs:$rx, imm_type:$imm16)>; 1431 <(brcond (i32 (seteq CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1432 (BteqzT8CmpX16 CPU16Regs:$rx, CPU16Regs:$ry, bb:$imm16) 1450 <(brcond (i32 (setgt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), [all …]
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D | MicroMipsInstrFormats.td | 301 bits<16> imm16; 308 let Inst{15-0} = imm16; 314 bits<16> imm16; 321 let Inst{15-0} = imm16; 326 bits<16> imm16; 333 let Inst{15-0} = imm16; 668 bits<16> imm16; 675 let Inst{15-0} = imm16;
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D | MicroMips64r6InstrFormats.td | 124 bits<16> imm16; 131 let Inst{15-0} = imm16;
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D | MicroMips32r6InstrFormats.td | 167 bits<16> imm16; 174 let Inst{15-0} = imm16; 487 bits<16> imm16; 494 let Inst{15-0} = imm16;
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/external/llvm/lib/Target/Lanai/ |
D | LanaiInstrInfo.td | 280 def LO : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, LoExt:$imm16), 281 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"), 284 def HI : InstRI<subOp, (outs GPR:$Rd), (ins GPR:$Rs1, HiExt:$imm16), 285 !strconcat(AsmStr, "\t$Rs1, $imm16, $Rd"), 304 [(set GPR:$Rd, (OpNode GPR:$Rs1, LoExt:$imm16))], 305 [(set GPR:$Rd, (OpNode GPR:$Rs1, HiExt:$imm16))]>; 411 def MOVHI : InstRI<0b000, (outs GPR:$Rd), (ins i32hi16:$imm16), 412 "mov\t$imm16, $Rd", 413 [(set GPR:$Rd, i32hi16:$imm16)]>; 415 def : InstAlias<"mov $imm16, $dst", (ADD_I_LO GPR:$dst, R0, i32lo16z:$imm16)>; [all …]
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D | LanaiInstrFormats.td | 95 bits<16> imm16; 103 let Inst{15 - 0} = imm16; 203 bits<16> imm16; 214 let Inst{15 - 0} = imm16; 360 bits<16> imm16; 367 let Inst{15 - 0} = imm16;
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/external/valgrind/none/tests/amd64/ |
D | insn_basic.def | 15 ###adcw eflags[0x1,0x0] : imm16[1234] ax.uw[5678] => 1.uw[6912] 16 ###adcw eflags[0x1,0x1] : imm16[1234] ax.uw[5678] => 1.uw[6913] 17 adcw eflags[0x1,0x0] : imm16[1234] bx.uw[5678] => 1.uw[6912] 18 adcw eflags[0x1,0x1] : imm16[1234] bx.uw[5678] => 1.uw[6913] 19 adcw eflags[0x1,0x0] : imm16[1234] m16.uw[5678] => 1.uw[6912] 20 adcw eflags[0x1,0x1] : imm16[1234] m16.uw[5678] => 1.uw[6913] 62 addw imm16[1234] ax.uw[5678] => 1.uw[6912] 63 addw imm16[1234] bx.uw[5678] => 1.uw[6912] 64 addw imm16[1234] m16.uw[5678] => 1.uw[6912] 89 andw imm16[0x4231] ax.uw[0x1234] => 1.uw[0x0230] [all …]
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/external/v8/src/ppc/ |
D | assembler-ppc.cc | 479 int imm16 = target_pos - pos; in target_at_put() local 480 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0); in target_at_put() 481 if (imm16 == kInstrSize && !(instr & kLKMask)) { in target_at_put() 486 instr |= (imm16 & kImm16Mask); in target_at_put() 746 int imm16 = branch_offset; in bc() local 747 CHECK(is_int16(imm16) && (imm16 & (kAAMask | kLKMask)) == 0); in bc() 748 emit(BCX | bo | condition_bit * B16 | (imm16 & kImm16Mask) | lk); in bc() 1023 intptr_t imm16 = src2.imm_; in cmpi() local 1029 DCHECK(is_int16(imm16)); in cmpi() 1031 imm16 &= kImm16Mask; in cmpi() [all …]
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/external/v8/src/x87/ |
D | assembler-x87.cc | 422 void Assembler::mov_w(const Operand& dst, int16_t imm16) { in mov_w() argument 427 EMIT(static_cast<int8_t>(imm16 & 0xff)); in mov_w() 428 EMIT(static_cast<int8_t>(imm16 >> 8)); in mov_w() 708 void Assembler::cmpw(const Operand& op, Immediate imm16) { in cmpw() argument 709 DCHECK(imm16.is_int16()); in cmpw() 714 emit_w(imm16); in cmpw() 1190 void Assembler::test_w(Register reg, Immediate imm16) { in test_w() argument 1191 DCHECK(imm16.is_int16() || imm16.is_uint16()); in test_w() 1195 emit_w(imm16); in test_w() 1200 emit_w(imm16); in test_w() [all …]
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D | assembler-x87.h | 611 void mov_w(const Operand& dst, int16_t imm16); 784 void test_w(Register reg, Immediate imm16); 785 void test_w(const Operand& op, Immediate imm16); 809 void ret(int imm16);
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | MipsInstrFormats.td | 109 bits<16> imm16; 115 let Inst{15-0} = imm16; 124 bits<16> imm16; 130 let Inst{15-0} = imm16; 194 bits<16> imm16; 200 let Inst{15-0} = imm16;
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D | MipsInstrInfo.td | 286 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 287 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), 288 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>; 292 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16), 293 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>; 334 FI<op, (outs CPURegs:$rt), (ins uimm16:$imm16), 335 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> { 402 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16), 403 !strconcat(instr_asm, "\t$rs, $rt, $imm16"), 404 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> { [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstr64Bit.td | 351 def napt : F2_4<cond, 0, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 352 !strconcat(OpcStr, " $rs1, $imm16"), []>; 353 def apt : F2_4<cond, 1, 1, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 354 !strconcat(OpcStr, ",a $rs1, $imm16"), []>; 355 def napn : F2_4<cond, 0, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 356 !strconcat(OpcStr, ",pn $rs1, $imm16"), []>; 357 def apn : F2_4<cond, 1, 0, (outs), (ins I64Regs:$rs1, bprtarget16:$imm16), 358 !strconcat(OpcStr, ",a,pn $rs1, $imm16"), []>; 362 def : InstAlias<!strconcat(OpcStr, ",pt $rs1, $imm16"), 363 (NAPT I64Regs:$rs1, bprtarget16:$imm16), 0>; [all …]
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D | SparcInstrFormats.td | 90 bits<16> imm16; 99 let Inst{21-20} = imm16{15-14}; 102 let Inst{13-0} = imm16{13-0};
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
D | MBlazeInstrFormats.td | 48 // imm16 - 16-bit immediate value. 114 bits<16> imm16; 118 let Inst{16-31} = imm16; 156 let imm16 = rimm16;
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/external/v8/src/ia32/ |
D | assembler-ia32.cc | 837 void Assembler::cmpw(const Operand& op, Immediate imm16) { in cmpw() argument 838 DCHECK(imm16.is_int16() || imm16.is_uint16()); in cmpw() 843 emit_w(imm16); in cmpw() 1319 void Assembler::test_w(Register reg, Immediate imm16) { in test_w() argument 1320 DCHECK(imm16.is_int16() || imm16.is_uint16()); in test_w() 1324 emit_w(imm16); in test_w() 1329 emit_w(imm16); in test_w() 1340 void Assembler::test_w(const Operand& op, Immediate imm16) { in test_w() argument 1341 DCHECK(imm16.is_int16() || imm16.is_uint16()); in test_w() 1343 test_w(op.reg(), imm16); in test_w() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
D | README.txt | 84 | Ksh | imm16 | | 144 | P+imm16 | | | | | | * | * | 163 | P+imm16 | | | | | * |
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D | BlackfinInstrInfo.td | 83 def imm16 : PatLeaf<(imm), [{return isInt<16>(N->getSExtValue());}]>; 201 [(set GR:$dst, imm16:$src)]>; 310 [(set D:$dst, (zextloadi8 (add P:$ptr, imm16:$off)))]>; 312 def : Pat<(i32 (extloadi8 (add P:$ptr, imm16:$off))), 314 def : Pat<(i16 (extloadi8 (add P:$ptr, imm16:$off))), 317 def : Pat<(i16 (zextloadi8 (add P:$ptr, imm16:$off))), 330 [(set D:$dst, (sextloadi8 (add P:$ptr, imm16:$off)))]>; 332 def : Pat<(i16 (sextloadi8 (add P:$ptr, imm16:$off))), 420 [(truncstorei8 D:$val, (add P:$ptr, imm16:$off))]>;
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/external/valgrind/VEX/priv/ |
D | host_mips_defs.c | 580 MIPSRH *MIPSRH_Imm(Bool syned, UShort imm16) in MIPSRH_Imm() argument 585 op->Mrh.Imm.imm16 = imm16; in MIPSRH_Imm() 589 vassert(imm16 != 0x8000); in MIPSRH_Imm() 608 vex_printf("%d", (Int) (Short) op->Mrh.Imm.imm16); in ppMIPSRH() 610 vex_printf("%u", (UInt) (UShort) op->Mrh.Imm.imm16); in ppMIPSRH() 2536 p = mkFormI(p, 9, r_srcL, r_dst, srcR->Mrh.Imm.imm16); in emit_MIPSInstr() 2546 vassert(srcR->Mrh.Imm.imm16 != 0x8000); in emit_MIPSInstr() 2547 p = mkFormI(p, 9, r_srcL, r_dst, (-srcR->Mrh.Imm.imm16)); in emit_MIPSInstr() 2557 p = mkFormI(p, 12, r_srcL, r_dst, srcR->Mrh.Imm.imm16); in emit_MIPSInstr() 2567 p = mkFormI(p, 13, r_srcL, r_dst, srcR->Mrh.Imm.imm16); in emit_MIPSInstr() [all …]
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/external/swiftshader/third_party/subzero/src/DartARM32/ |
D | assembler_arm.h | 606 void bkpt(uint16_t imm16); 608 static int32_t BkptEncoding(uint16_t imm16) { 611 ((imm16 >> 4) << 8) | B6 | B5 | B4 | (imm16 & 0xf); 1219 void movw(Register rd, uint16_t imm16, Condition cond = AL); 1221 void movt(Register rd, uint16_t imm16, Condition cond = AL);
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/external/v8/src/s390/ |
D | assembler-s390.cc | 379 int16_t imm16 = SIGN_EXT_IMM16((instr & kImm16Mask)); in target_at() local 380 imm16 <<= 1; // BRC immediate is in # of halfwords in target_at() 381 if (imm16 == 0) return kEndOfChain; in target_at() 382 return pos + imm16; in target_at() 409 int16_t imm16 = target_pos - pos; in target_at_put() local 411 DCHECK(is_int16(imm16)); in target_at_put() 412 instr_at_put<FourByteInstr>(pos, instr | (imm16 >> 1)); in target_at_put() 580 void Assembler::bkpt(uint32_t imm16) { in bkpt() argument
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