| /external/llvm/test/CodeGen/Mips/Fast-ISel/ |
| D | shftopm.ll | 26 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
27 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
44 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
64 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
65 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
81 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
100 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
101 ; CHECK-DAG: lhu $[[S2:[0-9]+]], 0($[[S2_ADDR]])
118 ; CHECK-DAG: lhu $[[S1:[0-9]+]], 0($[[S1_ADDR]])
|
| D | logopm.ll | 431 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
432 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
451 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
471 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
493 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
494 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
522 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
544 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
545 ; CHECK-DAG: lhu $[[US2:[0-9]+]], 0($[[US2_ADDR]])
564 ; CHECK-DAG: lhu $[[US1:[0-9]+]], 0($[[US1_ADDR]])
[all …]
|
| D | loadstoreconv.ll | 101 ; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
118 ; mips32r2: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
120 ; mips32: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
| D | retabi.ll | 34 ; CHECK: lhu $2, 0($[[REG_S_ADDR]])
48 ; CHECK: lhu $[[REG_S:[0-9]+]], 0($[[REG_S_ADDR]])
|
| D | bswap1.ll | 20 ; ALL: lhu $[[A_VAL:[0-9]+]], 0($[[A_ADDR]])
|
| D | loadstore2.ll | 40 ; CHECK: lhu $[[REGs:[0-9]+]], 0(${{[0-9]+}})
|
| /external/valgrind/none/tests/mips64/ |
| D | load_store.stdout.exp-BE | 14209 lhu :: offset: 0x0, out: 0x0
14210 lhu :: offset: 0x2, out: 0x0
14211 lhu :: offset: 0x4, out: 0x0
14212 lhu :: offset: 0x6, out: 0x0
14213 lhu :: offset: 0x8, out: 0x982
14214 lhu :: offset: 0xa, out: 0x3b6e
14215 lhu :: offset: 0xc, out: 0xd43
14216 lhu :: offset: 0xe, out: 0x26d9
14217 lhu :: offset: 0x10, out: 0x1304
14218 lhu :: offset: 0x12, out: 0x76dc
[all …]
|
| D | load_store.stdout.exp-LE | 14209 lhu :: offset: 0x0, out: 0x0
14210 lhu :: offset: 0x2, out: 0x0
14211 lhu :: offset: 0x4, out: 0x0
14212 lhu :: offset: 0x6, out: 0x0
14213 lhu :: offset: 0x8, out: 0x3b6e
14214 lhu :: offset: 0xa, out: 0x982
14215 lhu :: offset: 0xc, out: 0x26d9
14216 lhu :: offset: 0xe, out: 0xd43
14217 lhu :: offset: 0x10, out: 0x76dc
14218 lhu :: offset: 0x12, out: 0x1304
[all …]
|
| /external/llvm/test/CodeGen/Mips/cconv/ |
| D | return-struct.ll | 63 ; O32-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
65 ; O32-DAG: lhu $2, 0([[SP:\$sp]])
68 ; N32-LE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
73 ; N32-BE-DAG: lhu [[R2:\$[0-9]+]], %lo(struct_2byte)([[R1]])
79 ; N64-LE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]])
84 ; N64-BE-DAG: lhu [[R2:\$[0-9]+]], 0([[R1]])
103 ; O32-BE-DAG: lhu [[R1:\$[0-9]+]], 4([[PTR_LO]])
111 ; O32-LE-DAG: lhu $3, 4([[PTR_LO]])
125 ; N32-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR_LO]])
138 ; N64-BE-DAG: lhu [[R3:\$[0-9]+]], 4([[PTR]])
|
| /external/llvm/test/CodeGen/Mips/ |
| D | unalignedload.ll | 31 ; MIPS32R6-DAG: lhu $[[PART1:[0-9]+]], 2($[[R0]])
64 ; FIXME: We should be able to do better than this using lhu
66 ; MIPS32R6-EL-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
71 ; FIXME: We should be able to do better than this using lhu
73 ; MIPS32R6-EB-DAG: lhu $[[T0:[0-9]+]], 4($[[R2]])
|
| D | misha.ll | 32 ; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
33 ; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
|
| D | lhu1.ll | 12 ; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
|
| D | load-store-left-right.ll | 281 ; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
283 ; MIPS32R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
298 ; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 0($[[PTR]])
300 ; MIPS64R6-DAG: lhu $[[R1:[0-9]+]], 2($[[PTR]])
405 ; MIPS32R6-EL-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]])
410 ; MIPS32R6-EB-DAG: lhu $[[R2:[0-9]+]], 4($[[PTR]])
|
| D | mips64intldst.ll | 83 ; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]])
86 ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
|
| /external/llvm/test/MC/Mips/ |
| D | mips-memory-instructions.s | 30 # CHECK: lhu $4, 4($5) # encoding: [0x04,0x00,0xa4,0x94]
40 lhu $4, 4($5)
|
| D | micromips-loadstore-instructions.s | 15 # CHECK-EL: lhu $4, 8($2) # encoding: [0x82,0x34,0x08,0x00]
61 # CHECK-EB: lhu $4, 8($2) # encoding: [0x34,0x82,0x00,0x08]
104 lhu $4, 8($2)
|
| D | nacl-mask.s | 46 lhu $1, 0($4)
75 # CHECK-NEXT: lhu $1, 0($4)
|
| /external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
| D | mblaze_memory.s | 24 # CHECK: lhu
27 lhu r1, r2, r3
|
| /external/llvm/test/MC/Mips/micromips/ |
| D | invalid.s | 88 lhu $35, 8($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: invalid operand for instruction
92 …lhu $4, 8($35) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offs…
98 …lhu $4, -65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offs…
99 …lhu $4, 65536($2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: expected memory with 16-bit signed offs…
|
| /external/valgrind/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-mips32-LE | 196 lhu $t0, 0($t1) :: rt 0x00001e1f
197 lhu $t0, 4($t1) :: rt 0x00000000
198 lhu $t0, 8($t1) :: rt 0x00000003
199 lhu $t0, 12($t1) :: rt 0x0000ffff
200 lhu $t0, 16($t1) :: rt 0x00002e2f
201 lhu $t0, 20($t1) :: rt 0x00002b2b
202 lhu $t0, 24($t1) :: rt 0x00002e2b
203 lhu $t0, 28($t1) :: rt 0x00002d2a
204 lhu $t0, 32($t1) :: rt 0x00003f3e
205 lhu $t0, 36($t1) :: rt 0x00003d3c
[all …]
|
| D | MIPS32int.stdout.exp-mips32-BE | 196 lhu $t0, 0($t1) :: rt 0x0000121f
197 lhu $t0, 4($t1) :: rt 0x00000000
198 lhu $t0, 8($t1) :: rt 0x00000000
199 lhu $t0, 12($t1) :: rt 0x0000ffff
200 lhu $t0, 16($t1) :: rt 0x0000232f
201 lhu $t0, 20($t1) :: rt 0x0000242c
202 lhu $t0, 24($t1) :: rt 0x0000252a
203 lhu $t0, 28($t1) :: rt 0x0000262d
204 lhu $t0, 32($t1) :: rt 0x00003f34
205 lhu $t0, 36($t1) :: rt 0x00003e35
[all …]
|
| /external/llvm/test/CodeGen/Mips/llvm-ir/ |
| D | lh_lhu.ll | 28 ; CHECK: lhu $[[REG1:[0-9]+]], 0(${{[0-9]+}})
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/Mips/ |
| D | mips64intldst.ll | 81 ; CHECK-N64: lhu ${{[0-9]+}}, 0($[[R0]])
84 ; CHECK-N32: lhu ${{[0-9]+}}, 0($[[R0]])
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/MBlaze/ |
| D | mblaze_memory.txt | 16 # CHECK: lhu r1, r2, r3
|
| /external/llvm/test/MC/Mips/mips1/ |
| D | valid.s | 53 lhu $s3,-22851($v0)
161 lhu $3, %lo(g_8)($2) # CHECK: encoding: [0x94,0x43,A,A]
|