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Searched refs:load1 (Results 1 – 25 of 42) sorted by relevance

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/external/libvpx/libvpx/vpx_dsp/mips/
Ditrans32_dspr2.c36 int load1, load2, load3, load4; in idct32_rows_dspr2() local
147 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
207 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
267 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
323 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
379 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
435 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
661 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
720 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct32_rows_dspr2()
873 : [temp0] "=&r"(temp0), [load1] "=&r"(load1), [temp1] "=&r"(temp1), in idct32_rows_dspr2()
[all …]
Ditrans32_cols_dspr2.c32 int load1, load2, load3, load4; in vpx_idct32_cols_add_blk_dspr2() local
103 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
163 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
223 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
279 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
335 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
391 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
617 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
676 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in vpx_idct32_cols_add_blk_dspr2()
Dconvolve2_vert_dspr2.c30 uint32_t load1, load2; in convolve_bi_vert_4_dspr2() local
98 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_vert_4_dspr2()
120 uint32_t load1, load2; in convolve_bi_vert_64_dspr2() local
188 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_vert_64_dspr2()
Dconvolve2_avg_dspr2.c30 uint32_t load1, load2; in convolve_bi_avg_vert_4_dspr2() local
105 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_avg_vert_4_dspr2()
129 uint32_t load1, load2; in convolve_bi_avg_vert_64_dspr2() local
205 : [load1] "=&r"(load1), [load2] "=&r"(load2), [p1] "=&r"(p1), in convolve_bi_avg_vert_64_dspr2()
Dconvolve8_vert_dspr2.c30 uint32_t load1, load2, load3, load4; in convolve_vert_4_dspr2() local
152 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_vert_4_dspr2()
178 uint32_t load1, load2, load3, load4; in convolve_vert_64_dspr2() local
301 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_vert_64_dspr2()
Dconvolve8_avg_dspr2.c30 uint32_t load1, load2, load3, load4; in convolve_avg_vert_4_dspr2() local
160 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_avg_vert_4_dspr2()
186 uint32_t load1, load2, load3, load4; in convolve_avg_vert_64_dspr2() local
317 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in convolve_avg_vert_64_dspr2()
Ditrans16_dspr2.c25 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_rows_dspr2() local
67 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_rows_dspr2()
189 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_rows_dspr2()
400 int load1, load2, load3, load4, load5, load6, load7, load8; in idct16_cols_add_blk_dspr2() local
452 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_cols_add_blk_dspr2()
574 : [load1] "=&r"(load1), [load2] "=&r"(load2), [load3] "=&r"(load3), in idct16_cols_add_blk_dspr2()
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dpropagate_ir_flags.ll18 %load1 = load i32, i32* %idx1, align 4
23 %op1 = lshr exact i32 %load1, 1
44 %load1 = load i32, i32* %idx1, align 4
49 %op1 = lshr exact i32 %load1, 1
70 %load1 = load i32, i32* %idx1, align 4
75 %op1 = add nsw i32 %load1, 1
96 %load1 = load i32, i32* %idx1, align 4
101 %op1 = add nsw i32 %load1, 1
122 %load1 = load i32, i32* %idx1, align 4
127 %op1 = add nuw i32 %load1, 1
[all …]
Dpr27163.ll11 %load1 = load i64, i64* %gep1, align 8
13 store i64 %load1, i64* %gep1, align 8
27 %phi = phi i64 [ %load1, %catch.dispatch ], [ 9, %invoke.cont1 ]
/external/llvm/test/Transforms/LoadCombine/
Dload-combine-aa.ll11 %load1 = load i32, i32* %a, align 4
12 %conv = zext i32 %load1 to i64
14 store i32 %load1, i32* %b, align 4
29 %load1 = load i32, i32* %a, align 4
30 %conv = zext i32 %load1 to i64
32 store i32 %load1, i32* %b, align 4
Dload-combine-assume.ll15 %load1 = load i32, i32* %a, align 4
16 %conv = zext i32 %load1 to i64
34 %load1 = load i32, i32* %a, align 4
35 %conv = zext i32 %load1 to i64
/external/llvm/test/Transforms/CodeGenPrepare/AArch64/
Dfree-zext.ll11 %load1 = load i32, i32* %ptr, align 4
23 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %bb2 ]
36 %load1 = load i32, i32* %ptr, align 4
41 %trunc = trunc i32 %load1 to i16
46 %shl = shl i32 %load1, 16
53 %and = and i32 %load1, 65535
65 %load1 = load i32, i32* %ptr, align 4
70 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
/external/llvm/test/CodeGen/X86/
Daddr-mode-matcher.ll24 ; %load1 = (load (and (shl %xor, 2), 1020))
29 %load1 = load i32, i32* %tmp1704, align 4
40 ; While matching xor we address-match %load1. The and-of-shift reassocication
42 ; node becomes identical to %load2. CSE replaces %load1 which leaves its
44 %tmp1711 = xor i32 %load1, %tmp1710
Dadd-nsw-sext.ll155 %load1 = load i32, i32* %gep1, align 4
162 %add3 = add i32 %load1, %load2
/external/llvm/test/CodeGen/AArch64/
Dldst-opt.ll291 %load1 = load %pre.struct.i32*, %pre.struct.i32** %this
292 %gep1 = getelementptr inbounds %pre.struct.i32, %pre.struct.i32* %load1, i64 0, i32 1
309 %load1 = load %pre.struct.i64*, %pre.struct.i64** %this
310 %gep1 = getelementptr inbounds %pre.struct.i64, %pre.struct.i64* %load1, i64 0, i32 1
327 %load1 = load %pre.struct.i128*, %pre.struct.i128** %this
328 %gep1 = getelementptr inbounds %pre.struct.i128, %pre.struct.i128* %load1, i64 0, i32 1
345 %load1 = load %pre.struct.float*, %pre.struct.float** %this
346 %gep1 = getelementptr inbounds %pre.struct.float, %pre.struct.float* %load1, i64 0, i32 1
363 %load1 = load %pre.struct.double*, %pre.struct.double** %this
364 %gep1 = getelementptr inbounds %pre.struct.double, %pre.struct.double* %load1, i64 0, i32 1
[all …]
Darm64-vabs.ll37 %load1 = load <16 x i8>, <16 x i8>* %A
39 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
49 %load1 = load <8 x i16>, <8 x i16>* %A
51 … %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
61 %load1 = load <4 x i32>, <4 x i32>* %A
63 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
103 %load1 = load <16 x i8>, <16 x i8>* %A
105 …%tmp1 = shufflevector <16 x i8> %load1, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, …
116 %load1 = load <8 x i16>, <8 x i16>* %A
118 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
Dfree-zext.ll60 %load1 = load i32, i32* %ptr, align 4
63 %phi = phi i32 [ %load1, %bb1 ], [ %load2, %loop ]
Darm64-vmul.ll87 %load1 = load <8 x i16>, <8 x i16>* %A
89 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
98 %load1 = load <4 x i32>, <4 x i32>* %A
100 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
328 %load1 = load <8 x i16>, <8 x i16>* %A
331 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
341 %load1 = load <4 x i32>, <4 x i32>* %A
344 %tmp1 = shufflevector <4 x i32> %load1, <4 x i32> undef, <2 x i32> <i32 2, i32 3>
376 %load1 = load <8 x i16>, <8 x i16>* %A
379 %tmp1 = shufflevector <8 x i16> %load1, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dvselect.ll16 %load1 = load <2 x i32>, <2 x i32> addrspace(1)* %in1
17 %cmp = icmp sgt <2 x i32> %load0, %load1
58 %load1 = load <4 x i32>, <4 x i32> addrspace(1)* %in1
59 %cmp = icmp sgt <4 x i32> %load0, %load1
Dschedule-global-loads.ll17 %load1 = load i32, i32 addrspace(1)* %gep, align 4
19 store i32 %load1, i32 addrspace(1)* %out1, align 4
/external/mesa3d/src/compiler/nir/
Dnir_instr_set.c327 nir_load_const_instr *load1 = nir_instr_as_load_const(instr1); in nir_instrs_equal() local
330 if (load1->def.num_components != load2->def.num_components) in nir_instrs_equal()
333 if (load1->def.bit_size != load2->def.bit_size) in nir_instrs_equal()
336 return memcmp(load1->value.f32, load2->value.f32, in nir_instrs_equal()
337 load1->def.num_components * (load1->def.bit_size / 8u)) == 0; in nir_instrs_equal()
/external/llvm/test/CodeGen/PowerPC/
Dload-shift-combine.ll22 …%bf.load1 = load i96, i96* bitcast (%struct.S1847* getelementptr inbounds ([5 x %struct.S1847], [5…
23 %bf.clear2 = and i96 %bf.load1, 302231454903657293676543
/external/llvm/test/Instrumentation/AddressSanitizer/
Dexperiment-call.ll7 define void @load1(i8* %p) sanitize_address {
11 ; CHECK-LABEL: define void @load1
Dexperiment.ll7 define void @load1(i8* %p) sanitize_address {
11 ; CHECK-LABEL: define void @load1
/external/bart/docs/notebooks/thermal/
DThermal.ipynb174 "result = t.getStatement(\"((IN:load0 + IN:load1 + IN:load2 + IN:load3) == 0) \\\n",
182 "result = t.getStatement(\"((IN:load0 + IN:load1 + IN:load2 + IN:load3) == 0) \\\n",

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