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Searched refs:outw (Results 1 – 25 of 49) sorted by relevance

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/external/syslinux/gpxe/src/drivers/net/
D3c595.c77 outw(RX_DISABLE, BASE + VX_COMMAND); in t595_reset()
78 outw(RX_DISCARD_TOP_PACK, BASE + VX_COMMAND); in t595_reset()
80 outw(TX_DISABLE, BASE + VX_COMMAND); in t595_reset()
81 outw(STOP_TRANSCEIVER, BASE + VX_COMMAND); in t595_reset()
83 outw(RX_RESET, BASE + VX_COMMAND); in t595_reset()
85 outw(TX_RESET, BASE + VX_COMMAND); in t595_reset()
87 outw(C_INTR_LATCH, BASE + VX_COMMAND); in t595_reset()
88 outw(SET_RD_0_MASK, BASE + VX_COMMAND); in t595_reset()
89 outw(SET_INTR_MASK, BASE + VX_COMMAND); in t595_reset()
90 outw(SET_RX_FILTER, BASE + VX_COMMAND); in t595_reset()
[all …]
D3c5x9.c42 outw(RX_DISABLE, nic->ioaddr + EP_COMMAND); in t5x9_disable()
43 outw(RX_DISCARD_TOP_PACK, nic->ioaddr + EP_COMMAND); in t5x9_disable()
46 outw(TX_DISABLE, nic->ioaddr + EP_COMMAND); in t5x9_disable()
47 outw(STOP_TRANSCEIVER, nic->ioaddr + EP_COMMAND); in t5x9_disable()
49 outw(RX_RESET, nic->ioaddr + EP_COMMAND); in t5x9_disable()
50 outw(TX_RESET, nic->ioaddr + EP_COMMAND); in t5x9_disable()
51 outw(C_INTR_LATCH, nic->ioaddr + EP_COMMAND); in t5x9_disable()
52 outw(SET_RD_0_MASK, nic->ioaddr + EP_COMMAND); in t5x9_disable()
53 outw(SET_INTR_MASK, nic->ioaddr + EP_COMMAND); in t5x9_disable()
54 outw(SET_RX_FILTER, nic->ioaddr + EP_COMMAND); in t5x9_disable()
[all …]
D3c515.c100 outw(SelectWindow + (win_num), nic->ioaddr + EL3_CMD)
325 outw(TxReset, nic->ioaddr + EL3_CMD); in t515_reset()
330 outw(RxReset, nic->ioaddr + EL3_CMD); in t515_reset()
336 outw(SetStatusEnb | 0x00, nic->ioaddr + EL3_CMD); in t515_reset()
350 outw(0, nic->ioaddr + i); in t515_reset()
354 outw(StartCoax, nic->ioaddr + EL3_CMD); in t515_reset()
356 outw((inw(nic->ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) | in t515_reset()
370 outw(0x0040, nic->ioaddr + Wn4_NetDiag); in t515_reset()
395 outw(SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm, in t515_reset()
398 outw(RxEnable, nic->ioaddr + EL3_CMD); /* Enable the receiver. */ in t515_reset()
[all …]
Dcs89x0.c112 outw(portno, eth_nic_base + ADD_PORT); in readreg()
118 outw(portno, eth_nic_base + ADD_PORT); in writereg()
119 outw(value, eth_nic_base + DATA_PORT); in writereg()
275 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT); in send_test_pkt()
276 outw(ETH_ZLEN, eth_nic_base + TX_LEN_PORT); in send_test_pkt()
345 outw(PP_CS8920_ISAINT, eth_nic_base + ADD_PORT); in cs89x0_reset()
350 outw(PP_CS8920_ISAMemB, eth_nic_base + ADD_PORT); in cs89x0_reset()
381 outw(PP_ChipID, eth_nic_base + ADD_PORT); in cs89x0_reset()
407 outw(TX_AFTER_ALL, eth_nic_base + TX_CMD_PORT); in cs89x0_transmit()
408 outw(sr, eth_nic_base + TX_LEN_PORT); in cs89x0_transmit()
[all …]
Dsundance.c299 outw(inw(BASE + MACCtrl0) | EnbFullDuplex, in check_duplex()
312 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0, in check_duplex()
378 outw(addr16, BASE + StationAddr); in sundance_reset()
380 outw(addr16, BASE + StationAddr + 2); in sundance_reset()
382 outw(addr16, BASE + StationAddr + 4); in sundance_reset()
385 outw(sdc->mtu + 14, BASE + MaxFrameSize); in sundance_reset()
391 outw(0, BASE + DownCounter); in sundance_reset()
399 outw(RxEnable | TxEnable, BASE + MACCtrl1); in sundance_reset()
433 outw(intr_status, nic->ioaddr + IntrEnable); in sundance_irq()
436 outw(0x0200, BASE + ASICCtrl); in sundance_irq()
[all …]
Deepro.c330 outw(rx_start = (RCV_LOWER_LIMIT << 8), nic->ioaddr + RCV_BAR); in eepro_reset()
331 outw(((RCV_UPPER_LIMIT << 8) | 0xFE), nic->ioaddr + RCV_STOP); in eepro_reset()
333 outw((RCV_LOWER_LIMIT << 8), nic->ioaddr + HOST_ADDRESS_REG); in eepro_reset()
334 outw(0, nic->ioaddr + IO_PORT); in eepro_reset()
336 outw((XMT_LOWER_LIMIT << 8), nic->ioaddr + xmt_bar); in eepro_reset()
359 outw(rcv_car, nic->ioaddr + HOST_ADDRESS_REG); in eepro_poll()
400 outw(rcv_car - 1, nic->ioaddr + RCV_STOP); in eepro_poll()
431 outw(last, nic->ioaddr + HOST_ADDRESS_REG); in eepro_transmit()
432 outw(XMT_CMD, nic->ioaddr + IO_PORT); in eepro_transmit()
433 outw(0, nic->ioaddr + IO_PORT); in eepro_transmit()
[all …]
Ddepca.c472 outw(CSR0, ioaddr + DEPCA_ADDR);\
473 outw(STOP, ioaddr + DEPCA_DATA)
504 outw(CSR1, nic->ioaddr + DEPCA_ADDR); /* initialisation block address LSW */
505 outw((u16) (lp.sh_mem & LA_MASK), nic->ioaddr + DEPCA_DATA);
506 outw(CSR2, nic->ioaddr + DEPCA_ADDR); /* initialisation block address MSW */
507 outw((u16) ((lp.sh_mem & LA_MASK) >> 16), nic->ioaddr + DEPCA_DATA);
508 outw(CSR3, nic->ioaddr + DEPCA_ADDR); /* ALE control */
509 outw(ACON, nic->ioaddr + DEPCA_DATA);
510 outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* Point back to CSR0 */
519 outw(CSR0, nic->ioaddr + DEPCA_ADDR); /* point back to CSR0 */
[all …]
Dtlan.h353 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead8()
363 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead16()
373 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioRead32()
383 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite8()
393 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite16()
394 outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); in TLan_DioWrite16()
403 outw(internal_addr, base_addr + TLAN_DIO_ADR); in TLan_DioWrite32()
D3c90x.c78 outw(val, ioaddr + regCommandIntStatus_w); in a3c90x_internal_IssueCommand()
160 outw(address, inf_3c90x->IOAddr + regEepromCommand_0_w); in a3c90x_internal_ReadEeprom()
215 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 0); in a3c90x_reset()
216 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 2); in a3c90x_reset()
217 outw(0, inf_3c90x->IOAddr + regStationMask_2_3w + 4); in a3c90x_reset()
625 outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); in a3c90x_remove()
626 outw(cmdTxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); in a3c90x_remove()
674 outw(tmp, inf_3c90x->IOAddr + regResetOptions_2_w); in a3c90x_hw_start()
849 outw(cmdRxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); in a3c90x_close()
850 outw(cmdTxDisable, inf_3c90x->IOAddr + regCommandIntStatus_w); in a3c90x_close()
Dsmc9000.c49 # define _outw outw
149 outw( mii_reg | bits[i], ioaddr+MII_REG ); in smc_read_phy_register()
154 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG ); in smc_read_phy_register()
161 outw( mii_reg, ioaddr+MII_REG ); in smc_read_phy_register()
273 outw( mii_reg | bits[i], ioaddr+MII_REG ); in smc_write_phy_register()
278 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG ); in smc_write_phy_register()
285 outw( mii_reg, ioaddr+MII_REG ); in smc_write_phy_register()
405 outw( rpc_cur_mode, ioaddr + RPC_REG ); in smc_phy_configure()
501 outw( rpc_cur_mode, ioaddr + RPC_REG ); in smc_phy_configure()
Dvia-rhine.c867 outw (ReadMIItmp, wMIIDATA); in WriteMII()
953 outw(intr_status, nic->ioaddr + IntrEnable); in rhine_irq()
956 outw(0x0010, nic->ioaddr + 0x84); in rhine_irq()
1039 outw(CR_SFRST, byCR0); in rhine_probe1()
1132 outw (CR_FDX, byCR0); in rhine_probe1()
1184 outw(CR_STOP, byCR0); in rhine_disable()
1274 outw (CR_FDX, byCR0); in rhine_reset()
1280 outw ((CRbak | CR_STRT | CR_TXON | CR_RXON | CR_DPOLL), byCR0); in rhine_reset()
1283 outw (0, byIMR0); in rhine_reset()
1310 outw(intr_status & 0xffff, nic->ioaddr + IntrStatus); in rhine_poll()
[all …]
Dpcnet32.c268 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_read_csr()
274 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_csr()
275 outw(val, addr + PCNET32_WIO_RDP); in pcnet32_wio_write_csr()
280 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_read_bcr()
286 outw(index, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_bcr()
287 outw(val, addr + PCNET32_WIO_BDP); in pcnet32_wio_write_bcr()
297 outw(val, addr + PCNET32_WIO_RAP); in pcnet32_wio_write_rap()
307 outw(88, addr + PCNET32_WIO_RAP); in pcnet32_wio_check()
Dtlan.c340 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); in TLan_ResetAdapter()
507 outw(host_int, BASE + TLAN_HOST_INT); in tlan_poll()
838 outw(data, BASE + TLAN_HOST_CMD); in tlan_probe()
885 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); in TLan_EeSendStart()
924 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); in TLan_EeSendByte()
981 outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR); in TLan_EeReceiveByte()
1107 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); in TLan_MiiReadReg()
1185 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR); in TLan_MiiSendData()
1221 outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR); in TLan_MiiSync()
1257 outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR); in TLan_MiiWriteReg()
Dpnic.c54 outw ( input_length, pnic->ioaddr + PNIC_REG_LEN ); in pnic_command_quiet()
59 outw ( command, pnic->ioaddr + PNIC_REG_CMD ); in pnic_command_quiet()
Drtl8139.c421 outw ( status, rtl->ioaddr + IntrStatus ); in rtl_poll()
470 outw ( rtl->rx.offset - 16, rtl->ioaddr + RxBufPtr ); in rtl_poll()
485 outw ( ( enable ? ( ROK | RER | TOK | TER ) : 0 ), in rtl_irq()
Deepro100.c270 outw ( intr_status, ioaddr + SCBStatus ); in ifec_net_close()
297 outw ( enable ? INTERRUPT_MASK : SCBMaskAll, ioaddr + SCBCmd ); in ifec_net_irq()
410 outw ( intr_status, priv->ioaddr + SCBStatus ); in ifec_net_poll()
532 outw ( val, ee_addr ); in ifec_spi_write_bit()
Dnatsemi.c313 outw (pmatch[i], np->ioaddr + RxFilterData); in natsemi_reset()
317 outw (sopass[i], np->ioaddr + RxFilterData); in natsemi_reset()
348 outw (netdev->ll_addr[i] + (netdev->ll_addr[i + 1] << 8), in natsemi_open()
Ddmfe.c595 outw(addrptr[0], ioaddr); in dm9132_id_table()
597 outw(addrptr[1], ioaddr); in dm9132_id_table()
599 outw(addrptr[2], ioaddr); in dm9132_id_table()
617 outw(hash_table[i], ioaddr); in dm9132_id_table()
887 outw(phy_data, ioaddr); in phy_write()
/external/syslinux/gpxe/src/include/gpxe/
Dvirtio-pci.h81 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_NOTIFY); in vp_notify()
88 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL); in vp_del_vq()
Dio.h337 void outw ( uint16_t data, volatile uint16_t *io_addr );
338 #define outw( data, io_addr ) \ macro
339 IOAPI_WRITE ( outw, uint16_t, data, io_addr, "IO", 4 )
488 #define outw_p( data, io_addr ) OUTX_P ( outw, data, io_addr )
/external/libchrome/base/strings/
Dstringprintf_unittest.cc97 std::wstring outw; in TEST() local
98 SStringPrintf(&outw, L"%ls", srcw); in TEST()
99 EXPECT_STREQ(srcw, outw.c_str()); in TEST()
/external/syslinux/gpxe/src/drivers/bus/
Dvirtio-pci.c27 outw(queue_index, ioaddr + VIRTIO_PCI_QUEUE_SEL); in vp_find_vq()
/external/syslinux/com32/include/sys/
Dio.h32 static inline void outw(uint16_t v, uint16_t p) in outw() function
/external/syslinux/gpxe/src/arch/i386/core/
Dx86_io.c87 PROVIDE_IOAPI_INLINE ( x86, outw );
/external/syslinux/gpxe/src/arch/x86/include/gpxe/
Dpcidirect.h120 outw ( value, PCIDIRECT_CONFIG_DATA + ( where & 2 ) ); in PCIAPI_INLINE()

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