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Searched refs:s_mov_b32 (Results 1 – 25 of 70) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dsop1-err.s5 s_mov_b32 v1, s2 label
8 s_mov_b32 s1, v0 label
11 s_mov_b32 s[1:2], s0 label
14 s_mov_b32 s0, s[1:2] label
17 s_mov_b32 s220, s0 label
20 s_mov_b32 s0, s220 label
30 s_mov_b32 s1, 0xfffffffff label
41 s_mov_b32 s label
45 s_mov_b32 s102, 1 label
49 s_mov_b32 s103, 1 label
Dexpressions.s8 s_mov_b32 s0, global label
17 s_mov_b32 s0, gds label
22 s_mov_b32 s0, gds+4 label
35 s_mov_b32 s0, foo+2 label
40 s_mov_b32 s0, foo+2 label
Dtrap.s69 s_mov_b32 m0, ttmp8 label
73 s_mov_b32 ttmp10, 0 label
77 s_mov_b32 ttmp11, 0x01024fac label
81 s_mov_b32 ttmp8, m0 label
85 s_mov_b32 ttmp8, tma_lo label
Dsop1.s6 s_mov_b32 s1, s2 label
10 s_mov_b32 s1, 1 label
14 s_mov_b32 s1, 100 label
19 s_mov_b32 s1, 0x80000000 label
24 s_mov_b32 s0, 0xfe5163ab label
Dflat-scratch.s12 s_mov_b32 flat_scratch_lo, -1 label
17 s_mov_b32 flat_scratch_hi, -1 label
33 s_mov_b32 flat_scratch, -1 label
Dreloc.s10 s_mov_b32 s0, SCRATCH_RSRC_DWORD0
11 s_mov_b32 s1, SCRATCH_RSRC_DWORD1
12 s_mov_b32 s2, global_var@GOTPCREL
/external/llvm/test/CodeGen/AMDGPU/
Dlarge-alloca-graphics.ll5 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
6 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
7 ; GCN-DAG: s_mov_b32 s10, -1
8 ; CI-DAG: s_mov_b32 s11, 0xe8f000
9 ; VI-DAG: s_mov_b32 s11, 0xe80000
26 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
27 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
28 ; GCN-DAG: s_mov_b32 s10, -1
29 ; CI-DAG: s_mov_b32 s11, 0xe8f000
30 ; VI-DAG: s_mov_b32 s11, 0xe80000
Dwrite_register.ll37 ; CHECK: s_mov_b32 flat_scratch_lo, 0
38 ; CHECK: s_mov_b32 flat_scratch_lo, s{{[0-9]+}}
46 ; CHECK: s_mov_b32 flat_scratch_hi, 0
47 ; CHECK: s_mov_b32 flat_scratch_hi, s{{[0-9]+}}
55 ; CHECK: s_mov_b32 exec_lo, 0
56 ; CHECK: s_mov_b32 exec_lo, s{{[0-9]+}}
64 ; CHECK: s_mov_b32 exec_hi, 0
65 ; CHECK: s_mov_b32 exec_hi, s{{[0-9]+}}
Dconcat_vectors.ll9 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
18 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
27 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
36 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
45 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
54 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
63 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
72 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
81 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
90 ; SI-NOT: s_mov_b32 s{{[0-9]}}, 0x80f000
[all …]
Dlarge-alloca-compute.ll10 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
12 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
14 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, -1
15 ; CI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe8f000
16 ; VI-DAG: s_mov_b32 s{{[0-9]+}}, 0xe80000
Ds_movk_i32.ll5 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff{{$}}
44 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x8000{{$}}
57 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0x20000{{$}}
71 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0xff00ffff{{$}}
113 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
127 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
141 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
155 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
168 ; SI-DAG: s_mov_b32 [[LO_S_IMM:s[0-9]+]], 0xffff7001{{$}}
169 ; SI-DAG: s_mov_b32 [[HI_S_IMM:s[0-9]+]], 0x11111111{{$}}
Dindirect-addressing-si.ll12 ; CHECK: s_mov_b32 m0
32 ; CHECK: s_mov_b32 m0
48 ; CHECK: s_mov_b32 m0
108 ; CHECK: s_mov_b32 m0,
119 ; CHECK: s_mov_b32 m0
131 ; CHECK: s_mov_b32 m0
204 ; CHECK-DAG: s_mov_b32 [[S_ELT0:s[0-9]+]], 7
205 ; CHECK-DAG: s_mov_b32 [[S_ELT1:s[0-9]+]], 9
214 ; CHECK: s_mov_b32 m0, vcc_lo
227 ; CHECK: s_mov_b32 m0, vcc_lo
[all …]
Dllvm.AMDGPU.rsq.clamped.f64.ll11 ; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], -1
12 ; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
14 ; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
Dpromote-alloca-stored-pointer-value.ll28 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
29 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
43 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
44 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
Dfconst64.ll5 ; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0x40140000
6 ; CHECK-DAG: s_mov_b32 {{s[0-9]+}}, 0
Dllvm.amdgcn.rsq.clamp.ll28 ; VI-DAG: s_mov_b32 s[[LOW1:[0-9+]]], -1
29 ; VI-DAG: s_mov_b32 s[[HIGH1:[0-9+]]], 0x7fefffff
30 ; VI-DAG: s_mov_b32 s[[HIGH2:[0-9+]]], 0xffefffff
Dret.ll185 ; GCN: s_mov_b32 s2, s3
197 ; GCN: s_mov_b32 s0, 5
198 ; GCN-NOT: s_mov_b32 s0, s0
199 ; GCN-DAG: s_mov_b32 s1, 6
200 ; GCN-DAG: s_mov_b32 s2, 7
201 ; GCN-DAG: s_mov_b32 s3, 8
214 ; GCN-DAG: s_mov_b32 s1, s2
215 ; GCN: s_mov_b32 s2, s3
235 ; GCN-DAG: s_mov_b32 s0, 2
236 ; GCN-DAG: s_mov_b32 s1, 3
Dshl.ll221 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0xab19b207
234 ; SI-DAG: s_mov_b32 s[[KLO:[0-9]+]], 0x12d687{{$}}
235 ; SI-DAG: s_mov_b32 s[[KHI:[0-9]+]], 0{{$}}
338 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 4.0
339 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0{{$}}
349 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], -4.0
350 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], -1{{$}}
351 ; SI-DAG: s_mov_b32 s[[K_HI_COPY:[0-9]+]], s[[K_HI]]
361 ; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 4.0
362 ; SI-DAG: s_mov_b32 s[[K_LO:[0-9]+]], 0{{$}}
[all …]
Dfp_to_sint.f64.ll37 ; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
38 ; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
43 ; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
Dllvm.SI.sendmsg.ll5 ; CHECK: s_mov_b32 m0, 0
6 ; CHECK-NOT: s_mov_b32 m0
Dfp_to_uint.f64.ll37 ; CI-DAG: s_mov_b32 s[[K0_LO:[0-9]+]], 0{{$}}
38 ; CI-DAG: s_mov_b32 s[[K0_HI:[0-9]+]], 0x3df00000
43 ; CI-DAG: s_mov_b32 s[[K1_HI:[0-9]+]], 0xc1f00000
Dsubreg-coalescer-undef-use.ll19 ; CHECK-NEXT: s_mov_b32 s7, 0xf000
20 ; CHECK-NEXT: s_mov_b32 s6, -1
/external/clang/test/CodeGenOpenCL/
Damdgcn-flat-scratch-name.cl10 // CHECK: tail call void asm sideeffect "s_mov_b32 flat_scratch_lo, 0", "~{flat_scratch_lo}"()
11 __asm__ volatile("s_mov_b32 flat_scratch_lo, 0" : : : "flat_scratch_lo");
13 // CHECK: tail call void asm sideeffect "s_mov_b32 flat_scratch_hi, 0", "~{flat_scratch_hi}"()
14 __asm__ volatile("s_mov_b32 flat_scratch_hi, 0" : : : "flat_scratch_hi");
/external/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_vi.txt52 # VI: s_mov_b32 m0, ttmp8 ; encoding: [0x78,0x00,0xfc,0xbe]
55 # VI: s_mov_b32 ttmp10, 0 ; encoding: [0x80,0x00,0xfa,0xbe]
58 # VI: s_mov_b32 ttmp11, 0x1024fac ; encoding: [0xff,0x00,0xfb,0xbe,0xac,0x4f,0x02,0x01]
61 # VI: s_mov_b32 ttmp8, m0 ; encoding: [0x7c,0x00,0xf8,0xbe]
64 # VI: s_mov_b32 ttmp8, tma_lo ; encoding: [0x6e,0x00,0xf8,0xbe]
Dsop1_vi.txt3 # VI: s_mov_b32 s1, s2 ; encoding: [0x02,0x00,0x81,0xbe]
6 # VI: s_mov_b32 s1, 1 ; encoding: [0x81,0x00,0x81,0xbe]
9 # VI: s_mov_b32 s1, 0x64 ; encoding: [0xff,0x00,0x81,0xbe,0x64,0x00,0x00,0x00]
12 # VI: s_mov_b32 s1, 0x80000000 ; encoding: [0xff,0x00,0x81,0xbe,0x00,0x00,0x00,0x80]
15 # VI: s_mov_b32 s0, 0xfe5163ab ; encoding: [0xff,0x00,0x80,0xbe,0xab,0x63,0x51,0xfe]

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