Home
last modified time | relevance | path

Searched refs:s_mov_b64 (Results 1 – 25 of 25) sorted by relevance

/external/llvm/test/MC/AMDGPU/
Dreg-syntax-extra.s10 s_mov_b64 [ttmp4,ttmp5], [ttmp2,ttmp3] label
14 s_mov_b64 ttmp[4:5], ttmp[2:3] label
18 s_mov_b64 [s6,s7], s[8:9] label
22 s_mov_b64 s[6:7], [s8,s9] label
26 s_mov_b64 [exec_lo,exec_hi], s[2:3] label
30 s_mov_b64 [flat_scratch_lo,flat_scratch_hi], s[2:3] label
34 s_mov_b64 [vcc_lo,vcc_hi], s[2:3] label
38 s_mov_b64 [tba_lo,tba_hi], s[2:3] label
42 s_mov_b64 [tma_lo,tma_hi], s[2:3] label
Dtrap.s101 s_mov_b64 ttmp[4:5], exec label
105 s_mov_b64 [ttmp4,ttmp5], exec label
109 s_mov_b64 exec, [ttmp4,ttmp5] label
113 s_mov_b64 tba, ttmp[4:5] label
117 s_mov_b64 ttmp[4:5], tba label
121 s_mov_b64 tma, ttmp[4:5] label
125 s_mov_b64 ttmp[4:5], tma label
Dsop1-err.s23 s_mov_b64 s1, s[0:1] label
26 s_mov_b64 s[0:1], s1 label
34 s_mov_b64 s[0:1], 0xfffffffff label
37 s_mov_b64 s[0:1], 0x0000000200000000 label
53 s_mov_b64 s[102:103], -1 label
Dsop1.s28 s_mov_b64 s[2:3], s[4:5] label
32 s_mov_b64 s[2:3], 0xffffffffffffffff label
36 s_mov_b64 s[2:3], 0xffffffff label
40 s_mov_b64 s[0:1], 0x80000000 label
44 s_mov_b64 s[102:103], -1 label
Dflat-scratch.s7 s_mov_b64 flat_scratch, -1 label
23 s_mov_b64 flat_scratch_lo, -1 label
28 s_mov_b64 flat_scratch_hi, -1 label
Dout-of-range-registers.s16 s_mov_b64 s[0:17], -1 label
19 s_mov_b64 s[103:104], -1 label
22 s_mov_b64 s[104:105], -1 label
/external/llvm/test/CodeGen/AMDGPU/
Dwrite_register.ll15 ; CHECK: s_mov_b64 exec, 0
16 ; CHECK: s_mov_b64 exec, -1
17 ; CHECK: s_mov_b64 exec, s{{\[[0-9]+:[0-9]+\]}}
26 ; CHECK: s_mov_b64 flat_scratch, 0
27 ; CHECK: s_mov_b64 flat_scratch, -1
28 ; CHECK: s_mov_b64 flat_scratch, s{{\[[0-9]+:[0-9]+\]}}
Dwqm.ll37 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
59 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
84 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
89 ;CHECK: s_mov_b64 exec, [[SAVED]]
116 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
156 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
205 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
252 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
258 ;CHECK: s_mov_b64 exec, [[SAVE]]
281 ;CHECK-NEXT: s_mov_b64 [[ORIG:s\[[0-9]+:[0-9]+\]]], exec
[all …]
Dsmrd-vccz-bug.ll10 ; VCCZ-BUG: s_mov_b64 vcc, vcc
11 ; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc
Dvalu-i1.ll8 ; SI-NOT: s_mov_b64 s[{{[0-9]:[0-9]}}], -1
77 ; SI: s_mov_b64 {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
122 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0{{$}}
123 ; SI: s_mov_b64 [[COND_STATE:s\[[0-9]+:[0-9]+\]]], [[ZERO]]
Dllvm.amdgcn.ps.live.ll18 ; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
33 ; CHECK: s_mov_b64 [[LIVE:s\[[0-9]+:[0-9]+\]]], exec
Dllvm.amdgpu.kilp.ll5 ; SI: s_mov_b64 exec, 0
Dskip-if-dead.ll13 ; CHECK-NEXT: s_mov_b64 exec, 0
24 ; CHECK-NEXT: s_mov_b64 exec, 0
26 ; CHECK-NEXT: s_mov_b64 exec, 0
Dindirect-addressing-si.ll210 ; CHECK: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec
222 ; CHECK: s_mov_b64 exec, [[MASK]]
223 ; CHECK: s_mov_b64 [[MASK2:s\[[0-9]+:[0-9]+\]]], exec
266 ; CHECK: s_mov_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec
278 ; CHECK: s_mov_b64 exec, [[MASK]]
280 ; CHECK: s_mov_b64 [[MASK]], exec
Dllvm.AMDGPU.kill.ll6 ; SI: s_mov_b64 exec, 0
Dllvm.amdgcn.div.fmas.ll90 ; SI: s_mov_b64 vcc, 0
99 ; SI: s_mov_b64 vcc, -1
Doperand-folding.ll40 ; CHECK-NOT: s_mov_b64
Dsi-annotate-cf.ll31 ; SI: s_mov_b64 [[ZERO:s\[[0-9]+:[0-9]+\]]], 0
Dsalu-to-valu.ll17 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
18 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
/external/llvm/test/MC/Disassembler/AMDGPU/
Dtrap_vi.txt77 # VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
80 # VI: s_mov_b64 ttmp[4:5], exec ; encoding: [0x7e,0x01,0xf4,0xbe]
83 # VI: s_mov_b64 exec, ttmp[4:5] ; encoding: [0x74,0x01,0xfe,0xbe]
86 # VI: s_mov_b64 tba, ttmp[4:5] ; encoding: [0x74,0x01,0xec,0xbe]
89 # VI: s_mov_b64 ttmp[4:5], tba ; encoding: [0x6c,0x01,0xf4,0xbe]
92 # VI: s_mov_b64 tma, ttmp[4:5] ; encoding: [0x74,0x01,0xee,0xbe]
95 # VI: s_mov_b64 ttmp[4:5], tma ; encoding: [0x6e,0x01,0xf4,0xbe]
Dsop1_vi.txt18 # VI: s_mov_b64 s[2:3], s[4:5] ; encoding: [0x04,0x01,0x82,0xbe]
21 # FIXME: s_mov_b64 s[2:3], -1 ; encoding: [0xc1,0x01,0x82,0xbe]
24 # VI: s_mov_b64 s[2:3], 0xffffffff ; encoding: [0xff,0x01,0x82,0xbe,0xff,0xff,0xff,0xff]
27 # VI: s_mov_b64 s[0:1], 0x80000000 ; encoding: [0xff,0x01,0x80,0xbe,0x00,0x00,0x00,0x80]
/external/clang/test/CodeGenOpenCL/
Damdgcn-flat-scratch-name.cl7 // CHECK: tail call void asm sideeffect "s_mov_b64 flat_scratch, 0", "~{flat_scratch}"()
8 __asm__ volatile("s_mov_b64 flat_scratch, 0" : : : "flat_scratch");
/external/llvm/test/Object/AMDGPU/
Dobjdump.s20 s_mov_b64 s[2:3], exec
21 s_mov_b64 s[10:11], exec
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.td283 // Requires 2 s_mov_b64 to copy
301 // Requires 4 s_mov_b64 to copy
307 // Requires 8 s_mov_b64 to copy
DSIInstructions.td93 defm S_MOV_B64 : SOP1_64 <sop1<0x04, 0x01>, "s_mov_b64", []>;