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/external/llvm/test/CodeGen/PowerPC/
Dppc64-r2-alloc.ll7 %div = sdiv i32 %a, %d
8 %div1 = sdiv i32 %div, %d
9 %div2 = sdiv i32 %div1, %d
10 %div3 = sdiv i32 %div2, %d
11 %div4 = sdiv i32 %div3, %d
12 %div5 = sdiv i32 %div4, %d
13 %div6 = sdiv i32 %div5, %d
14 %div7 = sdiv i32 %div6, %d
15 %div8 = sdiv i32 %div7, %d
16 %div9 = sdiv i32 %div8, %d
[all …]
/external/llvm/test/Analysis/CostModel/X86/
Ddiv.ll7 ; SSE2: cost of 320 {{.*}} sdiv
8 %a0 = sdiv <16 x i8> undef, undef
9 ; SSE2: cost of 160 {{.*}} sdiv
10 %a1 = sdiv <8 x i16> undef, undef
11 ; SSE2: cost of 80 {{.*}} sdiv
12 %a2 = sdiv <4 x i32> undef, undef
13 ; SSE2: cost of 40 {{.*}} sdiv
14 %a3 = sdiv <2 x i32> undef, undef
21 ; AVX2: cost of 640 {{.*}} sdiv
22 %a0 = sdiv <32 x i8> undef, undef
[all …]
/external/llvm/test/Analysis/Lint/
Dcheck-zero-divide.ll4 %b = sdiv <2 x i32> %a, <i32 5, i32 8>
25 ; CHECK-NEXT: %b = sdiv i32 %a, 0
26 %b = sdiv i32 %a, 0
32 ; CHECK-NEXT: %b = sdiv i32 %a, 0
33 %b = sdiv i32 %a, zeroinitializer
39 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 0, i32 5>
40 %b = sdiv <2 x i32> %a, <i32 0, i32 5>
46 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, <i32 4, i32 0>
47 %b = sdiv <2 x i32> %a, <i32 4, i32 0>
53 ; CHECK-NEXT: %b = sdiv <2 x i32> %a, zeroinitializer
[all …]
/external/llvm/test/CodeGen/AArch64/
Darm64-neon-mul-div.ll104 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
105 %tmp3 = sdiv <1 x i8> %A, %B;
111 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
112 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
113 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
114 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
115 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
116 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
117 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
118 ; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
[all …]
Drem_crash.ll13 %0 = sdiv i8 %x, 10
29 %0 = sdiv i8 %x, 10
45 %0 = sdiv i16 %x, 10
61 %0 = sdiv i16 %x, 10
77 %0 = sdiv i32 %x, 10
93 %0 = sdiv i32 %x, 10
109 %0 = sdiv i64 %x, 10
125 %0 = sdiv i64 %x, 10
141 %0 = sdiv i8 %x, 10
157 %0 = sdiv i8 %x, 10
[all …]
Darm64-arith.ll33 ; CHECK: sdiv w0, w0, w1
35 %sdiv = sdiv i32 %a, %b
36 ret i32 %sdiv
42 ; CHECK: sdiv x0, x0, x1
44 %sdiv = sdiv i64 %a, %b
45 ret i64 %sdiv
170 ; CHECK: sdiv w0, w0, w1
172 %sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
173 ret i32 %sdiv
179 ; CHECK: sdiv x0, x0, x1
[all …]
Dsdivpow2.ll10 %div = sdiv i32 %x, 8
20 %div = sdiv i32 %x, -8
30 %div = sdiv i32 %x, 32
40 %div = sdiv i64 %x, 8
50 %div = sdiv i64 %x, -8
60 %div = sdiv i64 %x, 64
71 %div = sdiv i64 %x, 281474976710656
Dfast-isel-sdiv.ll7 %1 = sdiv exact i32 %a, 8
17 %1 = sdiv i32 %a, 8
27 %1 = sdiv i32 %a, -8
34 %1 = sdiv exact i64 %a, 16
44 %1 = sdiv i64 %a, 16
54 %1 = sdiv i64 %a, -16
Ddiv_minsize.ll5 %div = sdiv i32 %x, 32
8 ; CHECK: sdiv
13 %div = sdiv i32 %x, 33
16 ; CHECK: sdiv
42 %0 = sdiv <8 x i16> %var, <i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32, i16 32>
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Ddiv-vec.ll257 %res = sdiv <4 x i32> %v1, %v2
259 ; ASM: sdiv r0, r0, r1
260 ; ASM: sdiv r0, r0, r1
261 ; ASM: sdiv r0, r0, r1
262 ; ASM: sdiv r0, r0, r1
264 ; IASM-NOT: sdiv
274 %res = sdiv <8 x i16> %v1, %v2
278 ; ASM: sdiv r0, r0, r1
281 ; ASM: sdiv r0, r0, r1
284 ; ASM: sdiv r0, r0, r1
[all …]
/external/llvm/test/Analysis/CostModel/ARM/
Ddivrem.ll5 ; CHECK: cost of 40 {{.*}} sdiv
7 %1 = sdiv <2 x i8> %a, %b
12 ; CHECK: cost of 40 {{.*}} sdiv
14 %1 = sdiv <2 x i16> %a, %b
19 ; CHECK: cost of 40 {{.*}} sdiv
21 %1 = sdiv <2 x i32> %a, %b
26 ; CHECK: cost of 40 {{.*}} sdiv
28 %1 = sdiv <2 x i64> %a, %b
33 ; CHECK: cost of 10 {{.*}} sdiv
35 %1 = sdiv <4 x i8> %a, %b
[all …]
/external/llvm/test/CodeGen/ARM/
Drem_crash.ll13 %0 = sdiv i8 %x, 10
29 %0 = sdiv i8 %x, 10
45 %0 = sdiv i16 %x, 10
61 %0 = sdiv i16 %x, 10
77 %0 = sdiv i32 %x, 10
93 %0 = sdiv i32 %x, 10
109 %0 = sdiv i64 %x, 10
125 %0 = sdiv i64 %x, 10
141 %0 = sdiv i8 %x, 10
157 %0 = sdiv i8 %x, 10
[all …]
/external/llvm/test/CodeGen/X86/
Drem_crash.ll14 %0 = sdiv i8 %x, 10
30 %0 = sdiv i8 %x, 10
46 %0 = sdiv i16 %x, 10
62 %0 = sdiv i16 %x, 10
78 %0 = sdiv i32 %x, 10
94 %0 = sdiv i32 %x, 10
110 %0 = sdiv i64 %x, 10
126 %0 = sdiv i64 %x, 10
142 %0 = sdiv i8 %x, 10
158 %0 = sdiv i8 %x, 10
[all …]
Datom-bypass-slow-division.ll12 %result = sdiv i32 %a, %b
40 %resultdiv = sdiv i32 %a, %b
54 %resultidiv = sdiv i32 %a, %b
63 %resultdiv = sdiv i32 256, 4
72 %resultdiv = sdiv i32 %a, 33
90 %resultdiv = sdiv i32 %a, 33
101 %resultdiv = sdiv i32 4, %a
110 %resultdiv = sdiv i32 4, %a
/external/llvm/test/MC/ARM/
Didiv.s13 sdiv r1, r2, r3
15 @ A15-ARM: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
17 @ A15-THUMB: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
20 @ A15-ARM-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
22 @ A15-THUMB-NOARMHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
25 @ ARMV8: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
27 @ THUMBV8: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
30 @ ARMV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x12,0xf3,0x11,0xe7]
32 @ THUMBV8-NOTHUMBHWDIV: sdiv r1, r2, r3 @ encoding: [0x92,0xfb,0xf3,0xf1]
Dinvalid-idiv.s10 sdiv r1, r2, r3
13 @ ARM-A15: sdiv r1, r2, r3
17 @ THUMB-A15: sdiv r1, r2, r3
22 @ ARM: sdiv r1, r2, r3
26 @ THUMB: sdiv r1, r2, r3
/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/
Dexact.ll4 ; CHECK: sdiv i32 %x, 8
6 %y = sdiv i32 %x, 8
13 %y = sdiv exact i32 %x, 8
22 %y = sdiv i32 %x, 3
30 %y = sdiv exact i32 %x, 3
40 %y = sdiv i32 %x, 3
49 %y = sdiv exact i32 %x, 3
100 ; Make sure we don't transform the ashr here into an sdiv
126 %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
134 %A = sdiv exact i64 %X, 5 ; X/5 == 1 --> x == 5
[all …]
Dpreserve-sminmax.ll3 ; Instcombine normally would fold the sdiv into the comparison,
4 ; making "icmp slt i32 %h, 2", but in this case the sdiv has
10 %sd = sdiv i32 %h, 2
16 ; CHECK: %sd = sdiv i32 %h, 2
22 %sd = sdiv i32 %h, 2
28 ; CHECK: %sd = sdiv i32 %h, 2
D2008-02-16-SDivOverflow.ll5 %tmp1 = sdiv i32 %a, -1431655765
6 %tmp2 = sdiv i32 %tmp1, 3
11 %tmp1 = sdiv i8 %a, 64
12 %tmp2 = sdiv i8 %tmp1, 3
/external/llvm/test/Transforms/InstCombine/
Ddiv.ll10 %B = sdiv i32 %A, 1 ; <i32> [#uses=1]
29 %B = sdiv i32 0, %A ; <i32> [#uses=1]
39 %B = sdiv i32 %A, -1 ; <i32> [#uses=1]
132 %tmp3 = sdiv i32 %x, %x ; 1
170 ; CHECK-NEXT: [[DIV:%.*]] = sdiv <2 x i64> %x, <i64 -3, i64 -4>
174 %div = sdiv <2 x i64> %neg, <i64 3, i64 4>
183 %div = sdiv <2 x i64> %x, <i64 -1, i64 -1>
204 %A = sdiv i32 1, %x
210 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 %a, 3
214 %div = sdiv i32 %shl, 12
[all …]
Dpreserve-sminmax.ll3 ; Instcombine normally would fold the sdiv into the comparison,
4 ; making "icmp slt i32 %h, 2", but in this case the sdiv has
10 %sd = sdiv i32 %h, 2
16 ; CHECK: %sd = sdiv i32 %h, 2
22 %sd = sdiv i32 %h, 2
28 ; CHECK: %sd = sdiv i32 %h, 2
Dexact.ll6 ; CHECK-NEXT: [[Y:%.*]] = sdiv i32 %x, 8
9 %y = sdiv i32 %x, 8
18 %y = sdiv exact i32 %x, 8
27 %y = sdiv exact <2 x i32> %x, <i32 128, i32 128>
37 %y = sdiv i32 %x, 3
46 %y = sdiv exact i32 %x, 3
57 %y = sdiv i32 %x, 3
67 %y = sdiv exact i32 %x, 3
124 ; Make sure we don't transform the ashr here into an sdiv
163 %A = sdiv exact i64 %X, 5 ; X/5 == 0 --> x == 0
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dsdiv.ll5 ; The code generated by sdiv is long and complex and may frequently change.
9 ; opcodes generated by the sdiv lowering was being legalized and optimized to:
20 %result = sdiv i32 %num, %den
28 %result = sdiv i32 %num, 4
48 %result = sdiv i32 %num, 3435
57 %result = sdiv <2 x i32> %num, %den
64 %result = sdiv <2 x i32> %num, <i32 4, i32 4>
73 %result = sdiv <4 x i32> %num, %den
80 %result = sdiv <4 x i32> %num, <i32 4, i32 4, i32 4, i32 4>
93 %result = sdiv i8 %num, %den
[all …]
/external/llvm/test/CodeGen/SystemZ/
Dint-div-04.ll14 %div = sdiv i64 %a, %b
39 %div = sdiv i64 %a, %b
53 %div = sdiv i64 %a, %b
80 %div = sdiv i64 %a, %b
189 %div0 = sdiv i64 %ret, %val0
190 %div1 = sdiv i64 %div0, %val1
191 %div2 = sdiv i64 %div1, %val2
192 %div3 = sdiv i64 %div2, %val3
193 %div4 = sdiv i64 %div3, %val4
194 %div5 = sdiv i64 %div4, %val5
[all …]
Dint-div-01.ll14 %div = sdiv i32 %a, %b
41 %div = sdiv i32 %a, %b
56 %div = sdiv i32 %a, %b
73 %div = sdiv i32 %a, %b
87 %div = sdiv i32 %a, %b
116 %div = sdiv i32 %a, %b
205 %div = sdiv i32 %a, %b
239 %div0 = sdiv i32 %ret, %val0
240 %div1 = sdiv i32 %div0, %val1
241 %div2 = sdiv i32 %div1, %val2
[all …]

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