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1; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s
2; arm64 has its own copy of this because of the intrinsics
3
4define <8 x i8> @mul8xi8(<8 x i8> %A, <8 x i8> %B) {
5; CHECK-LABEL: mul8xi8:
6; CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
7	%tmp3 = mul <8 x i8> %A, %B;
8	ret <8 x i8> %tmp3
9}
10
11define <16 x i8> @mul16xi8(<16 x i8> %A, <16 x i8> %B) {
12; CHECK-LABEL: mul16xi8:
13; CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
14	%tmp3 = mul <16 x i8> %A, %B;
15	ret <16 x i8> %tmp3
16}
17
18define <4 x i16> @mul4xi16(<4 x i16> %A, <4 x i16> %B) {
19; CHECK-LABEL: mul4xi16:
20; CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h
21	%tmp3 = mul <4 x i16> %A, %B;
22	ret <4 x i16> %tmp3
23}
24
25define <8 x i16> @mul8xi16(<8 x i16> %A, <8 x i16> %B) {
26; CHECK-LABEL: mul8xi16:
27; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h
28	%tmp3 = mul <8 x i16> %A, %B;
29	ret <8 x i16> %tmp3
30}
31
32define <2 x i32> @mul2xi32(<2 x i32> %A, <2 x i32> %B) {
33; CHECK-LABEL: mul2xi32:
34; CHECK: mul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
35	%tmp3 = mul <2 x i32> %A, %B;
36	ret <2 x i32> %tmp3
37}
38
39define <4 x i32> @mul4x32(<4 x i32> %A, <4 x i32> %B) {
40; CHECK-LABEL: mul4x32:
41; CHECK: mul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
42	%tmp3 = mul <4 x i32> %A, %B;
43	ret <4 x i32> %tmp3
44}
45
46define <1 x i64> @mul1xi64(<1 x i64> %A, <1 x i64> %B) {
47; CHECK-LABEL: mul1xi64:
48; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
49  %tmp3 = mul <1 x i64> %A, %B;
50  ret <1 x i64> %tmp3
51}
52
53define <2 x i64> @mul2xi64(<2 x i64> %A, <2 x i64> %B) {
54; CHECK-LABEL: mul2xi64:
55; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
56; CHECK: mul x{{[0-9]+}}, x{{[0-9]+}}, x{{[0-9]+}}
57  %tmp3 = mul <2 x i64> %A, %B;
58  ret <2 x i64> %tmp3
59}
60
61 define <2 x float> @mul2xfloat(<2 x float> %A, <2 x float> %B) {
62; CHECK-LABEL: mul2xfloat:
63; CHECK: fmul {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
64	%tmp3 = fmul <2 x float> %A, %B;
65	ret <2 x float> %tmp3
66}
67
68define <4 x float> @mul4xfloat(<4 x float> %A, <4 x float> %B) {
69; CHECK-LABEL: mul4xfloat:
70; CHECK: fmul {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
71	%tmp3 = fmul <4 x float> %A, %B;
72	ret <4 x float> %tmp3
73}
74define <2 x double> @mul2xdouble(<2 x double> %A, <2 x double> %B) {
75; CHECK-LABEL: mul2xdouble:
76; CHECK: fmul {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
77	%tmp3 = fmul <2 x double> %A, %B;
78	ret <2 x double> %tmp3
79}
80
81
82 define <2 x float> @div2xfloat(<2 x float> %A, <2 x float> %B) {
83; CHECK-LABEL: div2xfloat:
84; CHECK: fdiv {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, {{v[0-9]+}}.2s
85	%tmp3 = fdiv <2 x float> %A, %B;
86	ret <2 x float> %tmp3
87}
88
89define <4 x float> @div4xfloat(<4 x float> %A, <4 x float> %B) {
90; CHECK-LABEL: div4xfloat:
91; CHECK: fdiv {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
92	%tmp3 = fdiv <4 x float> %A, %B;
93	ret <4 x float> %tmp3
94}
95define <2 x double> @div2xdouble(<2 x double> %A, <2 x double> %B) {
96; CHECK-LABEL: div2xdouble:
97; CHECK: fdiv {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
98	%tmp3 = fdiv <2 x double> %A, %B;
99	ret <2 x double> %tmp3
100}
101
102define <1 x i8> @sdiv1x8(<1 x i8> %A, <1 x i8> %B) {
103; CHECK-LABEL: sdiv1x8:
104; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
105	%tmp3 = sdiv <1 x i8> %A, %B;
106	ret <1 x i8> %tmp3
107}
108
109define <8 x i8> @sdiv8x8(<8 x i8> %A, <8 x i8> %B) {
110; CHECK-LABEL: sdiv8x8:
111; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
112; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
113; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
114; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
115; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
116; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
117; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
118; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
119	%tmp3 = sdiv <8 x i8> %A, %B;
120	ret <8 x i8> %tmp3
121}
122
123define <16 x i8> @sdiv16x8(<16 x i8> %A, <16 x i8> %B) {
124; CHECK-LABEL: sdiv16x8:
125; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
126; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
127; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
128; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
129; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
130; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
131; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
132; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
133; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
134; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
135; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
136; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
137; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
138; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
139; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
140; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
141	%tmp3 = sdiv <16 x i8> %A, %B;
142	ret <16 x i8> %tmp3
143}
144
145define <1 x i16> @sdiv1x16(<1 x i16> %A, <1 x i16> %B) {
146; CHECK-LABEL: sdiv1x16:
147; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
148	%tmp3 = sdiv <1 x i16> %A, %B;
149	ret <1 x i16> %tmp3
150}
151
152define <4 x i16> @sdiv4x16(<4 x i16> %A, <4 x i16> %B) {
153; CHECK-LABEL: sdiv4x16:
154; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
155; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
156; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
157; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
158	%tmp3 = sdiv <4 x i16> %A, %B;
159	ret <4 x i16> %tmp3
160}
161
162define <8 x i16> @sdiv8x16(<8 x i16> %A, <8 x i16> %B) {
163; CHECK-LABEL: sdiv8x16:
164; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
165; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
166; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
167; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
168; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
169; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
170; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
171; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
172	%tmp3 = sdiv <8 x i16> %A, %B;
173	ret <8 x i16> %tmp3
174}
175
176define <1 x i32> @sdiv1x32(<1 x i32> %A, <1 x i32> %B) {
177; CHECK-LABEL: sdiv1x32:
178; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
179	%tmp3 = sdiv <1 x i32> %A, %B;
180	ret <1 x i32> %tmp3
181}
182
183define <2 x i32> @sdiv2x32(<2 x i32> %A, <2 x i32> %B) {
184; CHECK-LABEL: sdiv2x32:
185; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
186; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
187	%tmp3 = sdiv <2 x i32> %A, %B;
188	ret <2 x i32> %tmp3
189}
190
191define <4 x i32> @sdiv4x32(<4 x i32> %A, <4 x i32> %B) {
192; CHECK-LABEL: sdiv4x32:
193; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
194; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
195; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
196; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
197	%tmp3 = sdiv <4 x i32> %A, %B;
198	ret <4 x i32> %tmp3
199}
200
201define <1 x i64> @sdiv1x64(<1 x i64> %A, <1 x i64> %B) {
202; CHECK-LABEL: sdiv1x64:
203; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
204	%tmp3 = sdiv <1 x i64> %A, %B;
205	ret <1 x i64> %tmp3
206}
207
208define <2 x i64> @sdiv2x64(<2 x i64> %A, <2 x i64> %B) {
209; CHECK-LABEL: sdiv2x64:
210; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
211; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
212	%tmp3 = sdiv <2 x i64> %A, %B;
213	ret <2 x i64> %tmp3
214}
215
216define <1 x i8> @udiv1x8(<1 x i8> %A, <1 x i8> %B) {
217; CHECK-LABEL: udiv1x8:
218; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
219	%tmp3 = udiv <1 x i8> %A, %B;
220	ret <1 x i8> %tmp3
221}
222
223define <8 x i8> @udiv8x8(<8 x i8> %A, <8 x i8> %B) {
224; CHECK-LABEL: udiv8x8:
225; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
226; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
227; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
228; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
229; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
230; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
231; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
232; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
233	%tmp3 = udiv <8 x i8> %A, %B;
234	ret <8 x i8> %tmp3
235}
236
237define <16 x i8> @udiv16x8(<16 x i8> %A, <16 x i8> %B) {
238; CHECK-LABEL: udiv16x8:
239; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
240; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
241; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
242; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
243; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
244; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
245; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
246; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
247; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
248; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
249; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
250; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
251; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
252; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
253; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
254; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
255	%tmp3 = udiv <16 x i8> %A, %B;
256	ret <16 x i8> %tmp3
257}
258
259define <1 x i16> @udiv1x16(<1 x i16> %A, <1 x i16> %B) {
260; CHECK-LABEL: udiv1x16:
261; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
262	%tmp3 = udiv <1 x i16> %A, %B;
263	ret <1 x i16> %tmp3
264}
265
266define <4 x i16> @udiv4x16(<4 x i16> %A, <4 x i16> %B) {
267; CHECK-LABEL: udiv4x16:
268; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
269; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
270; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
271; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
272	%tmp3 = udiv <4 x i16> %A, %B;
273	ret <4 x i16> %tmp3
274}
275
276define <8 x i16> @udiv8x16(<8 x i16> %A, <8 x i16> %B) {
277; CHECK-LABEL: udiv8x16:
278; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
279; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
280; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
281; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
282; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
283; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
284; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
285; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
286	%tmp3 = udiv <8 x i16> %A, %B;
287	ret <8 x i16> %tmp3
288}
289
290define <1 x i32> @udiv1x32(<1 x i32> %A, <1 x i32> %B) {
291; CHECK-LABEL: udiv1x32:
292; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
293	%tmp3 = udiv <1 x i32> %A, %B;
294	ret <1 x i32> %tmp3
295}
296
297define <2 x i32> @udiv2x32(<2 x i32> %A, <2 x i32> %B) {
298; CHECK-LABEL: udiv2x32:
299; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
300; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
301	%tmp3 = udiv <2 x i32> %A, %B;
302	ret <2 x i32> %tmp3
303}
304
305define <4 x i32> @udiv4x32(<4 x i32> %A, <4 x i32> %B) {
306; CHECK-LABEL: udiv4x32:
307; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
308; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
309; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
310; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
311	%tmp3 = udiv <4 x i32> %A, %B;
312	ret <4 x i32> %tmp3
313}
314
315define <1 x i64> @udiv1x64(<1 x i64> %A, <1 x i64> %B) {
316; CHECK-LABEL: udiv1x64:
317; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
318	%tmp3 = udiv <1 x i64> %A, %B;
319	ret <1 x i64> %tmp3
320}
321
322define <2 x i64> @udiv2x64(<2 x i64> %A, <2 x i64> %B) {
323; CHECK-LABEL: udiv2x64:
324; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
325; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
326	%tmp3 = udiv <2 x i64> %A, %B;
327	ret <2 x i64> %tmp3
328}
329
330define <1 x i8> @srem1x8(<1 x i8> %A, <1 x i8> %B) {
331; CHECK-LABEL: srem1x8:
332; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
333; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
334	%tmp3 = srem <1 x i8> %A, %B;
335	ret <1 x i8> %tmp3
336}
337
338define <8 x i8> @srem8x8(<8 x i8> %A, <8 x i8> %B) {
339; CHECK-LABEL: srem8x8:
340; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
341; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
342; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
343; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
344; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
345; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
346; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
347; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
348; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
349; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
350; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
351; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
352; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
353; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
354; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
355; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
356	%tmp3 = srem <8 x i8> %A, %B;
357	ret <8 x i8> %tmp3
358}
359
360define <16 x i8> @srem16x8(<16 x i8> %A, <16 x i8> %B) {
361; CHECK-LABEL: srem16x8:
362; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
363; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
364; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
365; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
366; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
367; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
368; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
369; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
370; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
371; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
372; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
373; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
374; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
375; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
376; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
377; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
378; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
379; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
380; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
381; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
382; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
383; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
384; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
385; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
386; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
387; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
388; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
389; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
390; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
391; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
392; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
393; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
394	%tmp3 = srem <16 x i8> %A, %B;
395	ret <16 x i8> %tmp3
396}
397
398define <1 x i16> @srem1x16(<1 x i16> %A, <1 x i16> %B) {
399; CHECK-LABEL: srem1x16:
400; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
401; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
402	%tmp3 = srem <1 x i16> %A, %B;
403	ret <1 x i16> %tmp3
404}
405
406define <4 x i16> @srem4x16(<4 x i16> %A, <4 x i16> %B) {
407; CHECK-LABEL: srem4x16:
408; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
409; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
410; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
411; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
412; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
413; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
414; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
415; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
416	%tmp3 = srem <4 x i16> %A, %B;
417	ret <4 x i16> %tmp3
418}
419
420define <8 x i16> @srem8x16(<8 x i16> %A, <8 x i16> %B) {
421; CHECK-LABEL: srem8x16:
422; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
423; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
424; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
425; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
426; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
427; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
428; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
429; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
430; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
431; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
432; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
433; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
434; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
435; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
436; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
437; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
438	%tmp3 = srem <8 x i16> %A, %B;
439	ret <8 x i16> %tmp3
440}
441
442define <1 x i32> @srem1x32(<1 x i32> %A, <1 x i32> %B) {
443; CHECK-LABEL: srem1x32:
444; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
445; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
446	%tmp3 = srem <1 x i32> %A, %B;
447	ret <1 x i32> %tmp3
448}
449
450define <2 x i32> @srem2x32(<2 x i32> %A, <2 x i32> %B) {
451; CHECK-LABEL: srem2x32:
452; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
453; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
454; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
455; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
456	%tmp3 = srem <2 x i32> %A, %B;
457	ret <2 x i32> %tmp3
458}
459
460define <4 x i32> @srem4x32(<4 x i32> %A, <4 x i32> %B) {
461; CHECK-LABEL: srem4x32:
462; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
463; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
464; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
465; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
466; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
467; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
468; CHECK: sdiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
469; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
470	%tmp3 = srem <4 x i32> %A, %B;
471	ret <4 x i32> %tmp3
472}
473
474define <1 x i64> @srem1x64(<1 x i64> %A, <1 x i64> %B) {
475; CHECK-LABEL: srem1x64:
476; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
477; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
478	%tmp3 = srem <1 x i64> %A, %B;
479	ret <1 x i64> %tmp3
480}
481
482define <2 x i64> @srem2x64(<2 x i64> %A, <2 x i64> %B) {
483; CHECK-LABEL: srem2x64:
484; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
485; CHECK: sdiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
486; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
487; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
488	%tmp3 = srem <2 x i64> %A, %B;
489	ret <2 x i64> %tmp3
490}
491
492define <1 x i8> @urem1x8(<1 x i8> %A, <1 x i8> %B) {
493; CHECK-LABEL: urem1x8:
494; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
495; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
496	%tmp3 = urem <1 x i8> %A, %B;
497	ret <1 x i8> %tmp3
498}
499
500define <8 x i8> @urem8x8(<8 x i8> %A, <8 x i8> %B) {
501; CHECK-LABEL: urem8x8:
502; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
503; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
504; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
505; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
506; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
507; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
508; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
509; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
510; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
511; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
512; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
513; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
514; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
515; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
516; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
517; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
518	%tmp3 = urem <8 x i8> %A, %B;
519	ret <8 x i8> %tmp3
520}
521
522define <16 x i8> @urem16x8(<16 x i8> %A, <16 x i8> %B) {
523; CHECK-LABEL: urem16x8:
524; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
525; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
526; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
527; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
528; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
529; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
530; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
531; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
532; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
533; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
534; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
535; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
536; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
537; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
538; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
539; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
540; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
541; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
542; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
543; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
544; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
545; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
546; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
547; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
548; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
549; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
550; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
551; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
552; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
553; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
554; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
555; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
556	%tmp3 = urem <16 x i8> %A, %B;
557	ret <16 x i8> %tmp3
558}
559
560define <1 x i16> @urem1x16(<1 x i16> %A, <1 x i16> %B) {
561; CHECK-LABEL: urem1x16:
562; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
563; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
564	%tmp3 = urem <1 x i16> %A, %B;
565	ret <1 x i16> %tmp3
566}
567
568define <4 x i16> @urem4x16(<4 x i16> %A, <4 x i16> %B) {
569; CHECK-LABEL: urem4x16:
570; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
571; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
572; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
573; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
574; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
575; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
576; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
577; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
578	%tmp3 = urem <4 x i16> %A, %B;
579	ret <4 x i16> %tmp3
580}
581
582define <8 x i16> @urem8x16(<8 x i16> %A, <8 x i16> %B) {
583; CHECK-LABEL: urem8x16:
584; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
585; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
586; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
587; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
588; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
589; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
590; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
591; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
592; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
593; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
594; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
595; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
596; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
597; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
598; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
599; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
600	%tmp3 = urem <8 x i16> %A, %B;
601	ret <8 x i16> %tmp3
602}
603
604define <1 x i32> @urem1x32(<1 x i32> %A, <1 x i32> %B) {
605; CHECK-LABEL: urem1x32:
606; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
607; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
608	%tmp3 = urem <1 x i32> %A, %B;
609	ret <1 x i32> %tmp3
610}
611
612define <2 x i32> @urem2x32(<2 x i32> %A, <2 x i32> %B) {
613; CHECK-LABEL: urem2x32:
614; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
615; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
616; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
617; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
618	%tmp3 = urem <2 x i32> %A, %B;
619	ret <2 x i32> %tmp3
620}
621
622define <4 x i32> @urem4x32(<4 x i32> %A, <4 x i32> %B) {
623; CHECK-LABEL: urem4x32:
624; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
625; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
626; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
627; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
628; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
629; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
630; CHECK: udiv {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
631; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
632	%tmp3 = urem <4 x i32> %A, %B;
633	ret <4 x i32> %tmp3
634}
635
636define <1 x i64> @urem1x64(<1 x i64> %A, <1 x i64> %B) {
637; CHECK-LABEL: urem1x64:
638; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
639; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
640	%tmp3 = urem <1 x i64> %A, %B;
641	ret <1 x i64> %tmp3
642}
643
644define <2 x i64> @urem2x64(<2 x i64> %A, <2 x i64> %B) {
645; CHECK-LABEL: urem2x64:
646; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
647; CHECK: udiv {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
648; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
649; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
650	%tmp3 = urem <2 x i64> %A, %B;
651	ret <2 x i64> %tmp3
652}
653
654define <2 x float> @frem2f32(<2 x float> %A, <2 x float> %B) {
655; CHECK-LABEL: frem2f32:
656; CHECK: bl fmodf
657; CHECK: bl fmodf
658	%tmp3 = frem <2 x float> %A, %B;
659	ret <2 x float> %tmp3
660}
661
662define <4 x float> @frem4f32(<4 x float> %A, <4 x float> %B) {
663; CHECK-LABEL: frem4f32:
664; CHECK: bl fmodf
665; CHECK: bl fmodf
666; CHECK: bl fmodf
667; CHECK: bl fmodf
668	%tmp3 = frem <4 x float> %A, %B;
669	ret <4 x float> %tmp3
670}
671
672define <1 x double> @frem1d64(<1 x double> %A, <1 x double> %B) {
673; CHECK-LABEL: frem1d64:
674; CHECK: bl fmod
675	%tmp3 = frem <1 x double> %A, %B;
676	ret <1 x double> %tmp3
677}
678
679define <2 x double> @frem2d64(<2 x double> %A, <2 x double> %B) {
680; CHECK-LABEL: frem2d64:
681; CHECK: bl fmod
682; CHECK: bl fmod
683	%tmp3 = frem <2 x double> %A, %B;
684	ret <2 x double> %tmp3
685}
686
687declare <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8>, <8 x i8>)
688declare <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8>, <16 x i8>)
689
690define <8 x i8> @poly_mulv8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
691; CHECK-LABEL: poly_mulv8i8:
692   %prod = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
693; CHECK: pmul v0.8b, v0.8b, v1.8b
694   ret <8 x i8> %prod
695}
696
697define <16 x i8> @poly_mulv16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
698; CHECK-LABEL: poly_mulv16i8:
699   %prod = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
700; CHECK: pmul v0.16b, v0.16b, v1.16b
701   ret <16 x i8> %prod
702}
703
704declare <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16>, <4 x i16>)
705declare <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16>, <8 x i16>)
706declare <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32>, <2 x i32>)
707declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)
708
709define <4 x i16> @test_sqdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
710; CHECK-LABEL: test_sqdmulh_v4i16:
711   %prod = call <4 x i16> @llvm.aarch64.neon.sqdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
712; CHECK: sqdmulh v0.4h, v0.4h, v1.4h
713   ret <4 x i16> %prod
714}
715
716define <8 x i16> @test_sqdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
717; CHECK-LABEL: test_sqdmulh_v8i16:
718   %prod = call <8 x i16> @llvm.aarch64.neon.sqdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
719; CHECK: sqdmulh v0.8h, v0.8h, v1.8h
720   ret <8 x i16> %prod
721}
722
723define <2 x i32> @test_sqdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
724; CHECK-LABEL: test_sqdmulh_v2i32:
725   %prod = call <2 x i32> @llvm.aarch64.neon.sqdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
726; CHECK: sqdmulh v0.2s, v0.2s, v1.2s
727   ret <2 x i32> %prod
728}
729
730define <4 x i32> @test_sqdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
731; CHECK-LABEL: test_sqdmulh_v4i32:
732   %prod = call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
733; CHECK: sqdmulh v0.4s, v0.4s, v1.4s
734   ret <4 x i32> %prod
735}
736
737declare <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16>, <4 x i16>)
738declare <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16>, <8 x i16>)
739declare <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32>, <2 x i32>)
740declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)
741
742define <4 x i16> @test_sqrdmulh_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
743; CHECK-LABEL: test_sqrdmulh_v4i16:
744   %prod = call <4 x i16> @llvm.aarch64.neon.sqrdmulh.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
745; CHECK: sqrdmulh v0.4h, v0.4h, v1.4h
746   ret <4 x i16> %prod
747}
748
749define <8 x i16> @test_sqrdmulh_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
750; CHECK-LABEL: test_sqrdmulh_v8i16:
751   %prod = call <8 x i16> @llvm.aarch64.neon.sqrdmulh.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
752; CHECK: sqrdmulh v0.8h, v0.8h, v1.8h
753   ret <8 x i16> %prod
754}
755
756define <2 x i32> @test_sqrdmulh_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
757; CHECK-LABEL: test_sqrdmulh_v2i32:
758   %prod = call <2 x i32> @llvm.aarch64.neon.sqrdmulh.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
759; CHECK: sqrdmulh v0.2s, v0.2s, v1.2s
760   ret <2 x i32> %prod
761}
762
763define <4 x i32> @test_sqrdmulh_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
764; CHECK-LABEL: test_sqrdmulh_v4i32:
765   %prod = call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
766; CHECK: sqrdmulh v0.4s, v0.4s, v1.4s
767   ret <4 x i32> %prod
768}
769
770declare <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float>, <2 x float>)
771declare <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float>, <4 x float>)
772declare <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double>, <2 x double>)
773
774define <2 x float> @fmulx_v2f32(<2 x float> %lhs, <2 x float> %rhs) {
775; CHECK-LABEL: fmulx_v2f32:
776; Using registers other than v0, v1 and v2 are possible, but would be odd.
777; CHECK: fmulx v0.2s, v0.2s, v1.2s
778        %val = call <2 x float> @llvm.aarch64.neon.fmulx.v2f32(<2 x float> %lhs, <2 x float> %rhs)
779        ret <2 x float> %val
780}
781
782define <4 x float> @fmulx_v4f32(<4 x float> %lhs, <4 x float> %rhs) {
783; CHECK-LABEL: fmulx_v4f32:
784; Using registers other than v0, v1 and v2 are possible, but would be odd.
785; CHECK: fmulx v0.4s, v0.4s, v1.4s
786        %val = call <4 x float> @llvm.aarch64.neon.fmulx.v4f32(<4 x float> %lhs, <4 x float> %rhs)
787        ret <4 x float> %val
788}
789
790define <2 x double> @fmulx_v2f64(<2 x double> %lhs, <2 x double> %rhs) {
791; CHECK-LABEL: fmulx_v2f64:
792; Using registers other than v0, v1 and v2 are possible, but would be odd.
793; CHECK: fmulx v0.2d, v0.2d, v1.2d
794        %val = call <2 x double> @llvm.aarch64.neon.fmulx.v2f64(<2 x double> %lhs, <2 x double> %rhs)
795        ret <2 x double> %val
796}
797
798