| /external/swiftshader/third_party/LLVM/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 247 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false; in ReverseBranchCondition()
248 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false; in ReverseBranchCondition()
249 case MBlaze::BGT: Cond[0].setImm(MBlaze::BLE); return false; in ReverseBranchCondition()
250 case MBlaze::BGE: Cond[0].setImm(MBlaze::BLT); return false; in ReverseBranchCondition()
251 case MBlaze::BLT: Cond[0].setImm(MBlaze::BGE); return false; in ReverseBranchCondition()
252 case MBlaze::BLE: Cond[0].setImm(MBlaze::BGT); return false; in ReverseBranchCondition()
253 case MBlaze::BEQI: Cond[0].setImm(MBlaze::BNEI); return false; in ReverseBranchCondition()
254 case MBlaze::BNEI: Cond[0].setImm(MBlaze::BEQI); return false; in ReverseBranchCondition()
255 case MBlaze::BGTI: Cond[0].setImm(MBlaze::BLEI); return false; in ReverseBranchCondition()
256 case MBlaze::BGEI: Cond[0].setImm(MBlaze::BLTI); return false; in ReverseBranchCondition()
[all …]
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| /external/llvm/lib/Target/AMDGPU/ |
| D | R600ClauseMergePass.cpp | 101 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
152 RootCFAlu.getOperand(Mode0Idx).setImm( in mergeIfPossible()
154 RootCFAlu.getOperand(KBank0Idx).setImm( in mergeIfPossible()
157 .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm()); in mergeIfPossible()
160 RootCFAlu.getOperand(Mode1Idx).setImm( in mergeIfPossible()
162 RootCFAlu.getOperand(KBank1Idx).setImm( in mergeIfPossible()
165 .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm()); in mergeIfPossible()
167 RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts); in mergeIfPossible()
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| D | R600InstrInfo.cpp | 784 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
800 PredSet->getOperand(2).setImm(Cond[1].getImm()); in InsertBranch()
949 MO.setImm(OPCODE_IS_NOT_ZERO_INT); in ReverseBranchCondition()
952 MO.setImm(OPCODE_IS_ZERO_INT); in ReverseBranchCondition()
955 MO.setImm(OPCODE_IS_NOT_ZERO); in ReverseBranchCondition()
958 MO.setImm(OPCODE_IS_ZERO); in ReverseBranchCondition()
995 MI.getOperand(8).setImm(0); in PredicateInstruction()
1383 MIB->getOperand(20).setImm(0); in buildSlotOfVectorInstruction()
1416 MI.getOperand(Idx).setImm(Imm); in setImmOperand()
1505 FlagOp.setImm(1); in addFlag()
[all …]
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| D | R600Packetizer.cpp | 226 MI->getOperand(LastOp).setImm(Bit); in setIsLastBit()
307 MI->getOperand(Op).setImm(BS[i]); in addToPacket()
311 MI.getOperand(Op).setImm(BS.back()); in addToPacket()
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| D | R600ControlFlowFinalizer.cpp | 449 ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1); in MakeALUClause()
469 Clause.first->getOperand(0).setImm(0); in EmitALUClause()
481 MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm()); in CounterPropagateAddr()
623 IfOrElseInst->getOperand(1).setImm(1); in runOnMachineFunction()
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| D | SIShrinkInstructions.cpp | 234 Src.setImm(ReverseImm); in runOnMachineFunction()
261 NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
| D | BlackfinRegisterInfo.cpp | 224 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
235 MI.getOperand(FIPos+1).setImm(-Offset); in eliminateFrameIndex()
297 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
309 MI.getOperand(FIPos+1).setImm(Offset); in eliminateFrameIndex()
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| /external/llvm/lib/Target/WebAssembly/ |
| D | WebAssemblyRegisterInfo.cpp | 74 MI.getOperand(FIOperandNum - 1).setImm(Offset); in eliminateFrameIndex()
95 ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset)); in eliminateFrameIndex()
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| D | WebAssemblySetP2AlignOperands.cpp | 104 MI.getOperand(3).setImm(P2Align); in runOnMachineFunction()
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| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| D | MachineOperand.h | 424 void setImm(int64_t immVal) { in setImm() function
473 Op.setImm(Val); in CreateImm()
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| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| D | MCInst.h | 73 void setImm(int64_t Val) { in setImm() function
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCMIPeephole.cpp | 158 MI.getOperand(3).setImm(3 - Immed); in simplifyCode()
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| D | PPCVSXSwapRemoval.cpp | 840 MI->getOperand(2).setImm(EltNo); in handleSpecialSwappables()
842 MI->getOperand(1).setImm(EltNo); in handleSpecialSwappables()
864 MI->getOperand(3).setImm(Selector); in handleSpecialSwappables()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMMCInstLower.cpp | 147 MCOp.setImm(Enc); in LowerARMMachineInstrToMCInst()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInstrInfo.cpp | 760 Operand.setImm(Operand.getImm() | innerLoopMask); in setInnerLoop()
766 Operand.setImm(Operand.getImm() | memReorderDisabledMask); in setMemReorderDisabled()
773 Operand.setImm(Operand.getImm() | memStoreReorderEnabledMask); in setMemStoreReorderEnabled()
789 Operand.setImm(Operand.getImm() | outerLoopMask); in setOuterLoop()
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| /external/llvm/include/llvm/MC/ |
| D | MCInst.h | 78 void setImm(int64_t Val) { in setImm() function
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZElimCompare.cpp | 292 AlterMasks[I]->setImm(CCValues); in adjustCCMasksForInstr()
295 AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) | in adjustCCMasksForInstr()
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| D | SystemZInstrInfo.cpp | 71 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); in splitMove()
100 OffsetMO.setImm(Offset); in splitAdjDynAlloc()
116 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm())); in expandRIPseudo()
391 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm()); in ReverseBranchCondition()
1179 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32); in expandPostRAPseudo()
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| D | SystemZShortenInst.cpp | 102 MI.getOperand(1).setImm(Imm >> 16); in shortenIIF()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineOperand.h | 508 void setImm(int64_t immVal) { in setImm() function
590 Op.setImm(Val); in CreateImm()
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| /external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 157 MI->getOperand(4).setImm((ME+1) & 31); in commuteInstruction()
158 MI->getOperand(5).setImm((MB-1) & 31); in commuteInstruction()
633 Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm())); in ReverseBranchCondition()
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| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 115 Instr.getOperand(2).setImm(0); in PostOperandDecodeAdjust()
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiRegisterInfo.cpp | 216 MI.getOperand(3).setImm(LPAC::SUB); in eliminateFrameIndex()
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| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| D | PTXFPRoundingModePass.cpp | 170 Op.setImm(Desc.second); in processInstruction()
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| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsMCCodeEmitter.cpp | 63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
110 InstIn.getOperand(2).setImm(pos - 32); in LowerDins()
116 InstIn.getOperand(3).setImm(size - 32); in LowerDins()
|