Home
last modified time | relevance | path

Searched refs:spills (Results 1 – 25 of 72) sorted by relevance

123

/external/llvm/test/CodeGen/Thumb2/
Daligned-spill.ll1 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=0 | FileCheck %s
2 ; RUN: llc < %s -mcpu=cortex-a8 -align-neon-spills=1 | FileCheck %s --check-prefix=NEON
27 ; Stack pointer must be updated before the spills.
32 ; This could legally happen before the spills.
58 ; Stack pointer must be updated before the spills.
85 ; Stack pointer must be updated before the spills.
/external/llvm/test/CodeGen/X86/
Dsink-cheap-instructions.ll2 ; RUN: llc < %s -mtriple=x86_64-linux -sink-insts-to-avoid-spills | FileCheck %s -check-prefix=SINK
5 ; spills.
D2003-08-03-CallArgLiveRanges.ll5 ; cause spills!
D2008-10-27-CoalescerBug.ll3 ; Now this test spills one register. But a reload in the loop is cheaper than
Dmusttail-varargs.ll9 ; spill around it. A simple adjustment should not require any XMM spills.
118 ; This thunk shouldn't require any spills and reloads, assuming the register
Dstatepoint-stackmap-format.ll15 ; Do we see two spills for the local values and the store to the
44 ; Do we see two spills for the local values and the store to the
/external/llvm/test/CodeGen/AMDGPU/
Dspill-scavenge-offset.ll8 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
10 ; mechanism works even when many spills happen.
/external/llvm/test/CodeGen/SystemZ/
Dalias-01.ll5 ; Check that there are no spills.
/external/swiftshader/third_party/LLVM/test/CodeGen/X86/
D2003-08-03-CallArgLiveRanges.ll4 ; cause spills!
Dpmul.ll23 ; Use a call to force spills.
D2008-10-27-CoalescerBug.ll2 ; Now this test spills one register. But a reload in the loop is cheaper than
Dpr3495-2.ll5 ; It used to have two spills and four reloads, but not it only has one spill and one reload.
/external/llvm/test/CodeGen/SPARC/
Dspillsize.ll6 ; This function spills two values: %p and the materialized large constant.
Dspill.ll3 ;; Ensure that spills and reloads work for various types on
/external/llvm/test/CodeGen/PowerPC/
Dframe-size.ll11 ; will fail the small-frame-size check and the function has spills).
/external/llvm/test/Transforms/SLPVectorizer/AArch64/
Dload-store-q.ll6 ; spills and fills. This is the case for <2 x double>,
/external/llvm/test/CodeGen/ARM/
Dgpr-paired-spill-thumbinst.ll4 ; This test makes sure spills of 64-bit pairs in Thumb mode actually
Dvector-spilling.ll5 ; This test will generate spills/fills using vldmia instructions that access 24 bytes of memory.
Dneon_spill.ll5 ; This test case spills a QQQQ register.
Dgpr-paired-spill.ll26 ; offset from sp can be generated), so we need two spills.
Dsubreg-remat.ll10 ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
/external/swiftshader/third_party/subzero/tests_lit/assembler/arm32/
Dload-store.ll1 ; Show that we can handle variable (i.e. stack) spills.
/external/llvm/test/CodeGen/AArch64/
Darm64-zero-cycle-zeroing.ll59 ; We used to produce spills+reloads for a Q register with zero cycle zeroing
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dsubreg-remat.ll10 ; When %vreg6 spills, the VLDRS constant pool load cannot be rematerialized
/external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/
D2009-12-17-pre-regalloc-taildup.ll5 ; This test should not produce any spills, even when tail duplication creates lots of phi nodes.

123