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Searched refs:splat (Results 1 – 25 of 97) sorted by relevance

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/external/llvm/test/CodeGen/SystemZ/
Dvec-perm-01.ll1 ; Test vector splat.
5 ; Test v16i8 splat of the first element.
15 ; Test v16i8 splat of the last element.
28 ; Test v16i8 splat of an arbitrary element, using the second operand of
42 ; Test v8i16 splat of the first element.
52 ; Test v8i16 splat of the last element.
63 ; Test v8i16 splat of an arbitrary element, using the second operand of
75 ; Test v4i32 splat of the first element.
85 ; Test v4i32 splat of the last element.
95 ; Test v4i32 splat of an arbitrary element, using the second operand of
[all …]
Dvec-perm-02.ll5 ; Test v16i8 splat of the first element.
17 ; Test v16i8 splat of the last element.
32 ; Test v16i8 splat of an arbitrary element, using the second operand of
48 ; Test v8i16 splat of the first element.
60 ; Test v8i16 splat of the last element.
73 ; Test v8i16 splat of an arbitrary element, using the second operand of
87 ; Test v4i32 splat of the first element.
99 ; Test v4i32 splat of the last element.
111 ; Test v4i32 splat of an arbitrary element, using the second operand of
124 ; Test v2i64 splat of the first element.
[all …]
Dvec-combine-01.ll43 ; ...and again in a case where there's also a splat and a bitcast.
53 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
55 %splatcast = bitcast <2 x i64> %splat to <4 x i32>
75 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
77 %splatcast = bitcast <2 x i64> %splat to <4 x i32>
97 %splat = shufflevector <2 x i64> %v3, <2 x i64> undef,
99 %splatcast = bitcast <2 x i64> %splat to <4 x i32>
/external/llvm/test/CodeGen/Mips/msa/
D3r_splat.ll1 ; Test the MSA splat intrinsics that are encoded with the 3R instruction
15 %1 = tail call <16 x i8> @llvm.mips.splat.b(<16 x i8> %0, i32 %a)
20 declare <16 x i8> @llvm.mips.splat.b(<16 x i8>, i32) nounwind
26 ; MIPS32-DAG: splat.b [[R4:\$w[0-9]+]], [[R3]][$4]
36 %1 = tail call <8 x i16> @llvm.mips.splat.h(<8 x i16> %0, i32 %a)
41 declare <8 x i16> @llvm.mips.splat.h(<8 x i16>, i32) nounwind
47 ; MIPS32-DAG: splat.h [[R4:\$w[0-9]+]], [[R3]][$4]
57 %1 = tail call <4 x i32> @llvm.mips.splat.w(<4 x i32> %0, i32 %a)
62 declare <4 x i32> @llvm.mips.splat.w(<4 x i32>, i32) nounwind
68 ; MIPS32-DAG: splat.w [[R4:\$w[0-9]+]], [[R3]][$4]
[all …]
Dllvm-stress-s2501752154-simplified.ll9 ; splat, but then proceeded to legalize the undef's to zero, leaving it as a
10 ; non-splat that cannot be selected. It should have eliminated the undef's by
11 ; rewriting the splat constant.
Dllvm-stress-s449609655-simplified.ll11 ; isVSplat() returned the splat value for <i8 -1, i8 -1, ...> as a 32-bit APInt
12 ; (255), but the zeroinitializer splat value as an 8-bit APInt (0). The
Dllvm-stress-s2090927243-simplified.ll8 ; splat, but are legalized to zero if left in the DAG which changes the constant
9 ; into a non-splat.
/external/llvm/test/Transforms/InstCombine/
Dfast-math-scalarization.ll8 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0
9 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
10 %splat.splatinsert1 = insertelement <4 x float> undef, float 3.0, i32 0
14 %x.0 = phi <4 x float> [ %splat.splat, %entry ], [ %mul, %for.body ]
Dvec_extract_elt.ll13 %splat = shufflevector <8 x i64> %vec, <8 x i64> undef, <8 x i32> zeroinitializer
14 %add = add <8 x i64> %splat, <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>
/external/llvm/test/CodeGen/AMDGPU/
Ddagcombiner-bug-illegal-vec4-int-to-fp.ll19 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
20 store <4 x float> %splat, <4 x float> addrspace(1)* %out
33 %splat = shufflevector <4 x float> %0, <4 x float> undef, <4 x i32> zeroinitializer
34 store <4 x float> %splat, <4 x float> addrspace(1)* %out
/external/llvm/test/CodeGen/ARM/
Dvdup.ll336 ; Check that an SPR splat produces a vdup.
342 %splat.splatinsert = insertelement <2 x float> undef, float %conv, i32 0
343 …%splat.splat = shufflevector <2 x float> %splat.splatinsert, <2 x float> undef, <2 x i32> zeroinit…
344 %sub = fsub <2 x float> %splat.splat, %p
352 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 0
353 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
354 %sub = fsub <4 x float> %splat.splat, %p
362 %splat.splatinsert = insertelement <4 x float> undef, float %conv, i32 1
363 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> <i32 1, …
364 %sub = fsub <4 x float> %splat.splat, %p
/external/llvm/test/CodeGen/X86/
Dsplat-const.ll19 %splat = shufflevector <4 x i32> %zero, <4 x i32> undef, <4 x i32> zeroinitializer
20 ret <4 x i32> %splat
38 %splat = shufflevector <4 x i32> %const, <4 x i32> undef, <4 x i32> zeroinitializer
39 ret <4 x i32> %splat
Davx2-vbroadcast.ll914 ; These tests check that a vbroadcast instruction is used when we have a splat
1011 %splat.splatinsert = insertelement <16 x i8> undef, i8 %tmp2, i32 0
1012 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial…
1013 %tmp3 = bitcast <16 x i8> %splat.splat to <2 x i64>
1030 %splat.splatinsert = insertelement <32 x i8> undef, i8 %tmp2, i32 0
1031 …%splat.splat = shufflevector <32 x i8> %splat.splatinsert, <32 x i8> undef, <32 x i32> zeroinitial…
1032 %tmp3 = bitcast <32 x i8> %splat.splat to <4 x i64>
1049 %splat.splatinsert = insertelement <8 x i16> undef, i16 %tmp2, i32 0
1050 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali…
1051 %tmp3 = bitcast <8 x i16> %splat.splat to <2 x i64>
[all …]
Dshl-i64.ll16 %splat = shufflevector <4 x i64> %3, <4 x i64> undef, <4 x i32> zeroinitializer
17 %shl = shl <4 x i64> %0, %splat
Dvector-shift-shl-512.ll100 %splat = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
101 %shift = shl <8 x i64> %a, %splat
112 %splat = shufflevector <16 x i32> %b, <16 x i32> undef, <16 x i32> zeroinitializer
113 %shift = shl <16 x i32> %a, %splat
134 %splat = shufflevector <32 x i16> %b, <32 x i16> undef, <32 x i32> zeroinitializer
135 %shift = shl <32 x i16> %a, %splat
166 %splat = shufflevector <64 x i8> %b, <64 x i8> undef, <64 x i32> zeroinitializer
167 %shift = shl <64 x i8> %a, %splat
/external/spirv-llvm/test/SPIRV/transcoding/
DOpConstantSampler.ll35 %splat.splatinsert = insertelement <4 x float> undef, float %1, i32 0
36 …%splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinit…
38 %mul = fmul <4 x float> %call6, %splat.splat
/external/skia/src/opts/
DSk4px_SSE2.h63 __m128i splat = _mm_set_epi8(15,15,15,15, 11,11,11,11, 7,7,7,7, 3,3,3,3); in alphas() local
64 return Sk16b(_mm_shuffle_epi8(this->fVec, splat)); in alphas()
69 __m128i splat = _mm_set_epi8(3,3,3,3, 2,2,2,2, 1,1,1,1, 0,0,0,0); in Load4Alphas() local
70 return Sk16b(_mm_shuffle_epi8(_mm_cvtsi32_si128(as), splat)); in Load4Alphas()
/external/llvm/test/CodeGen/PowerPC/
Dswaps-le-2.ll3 ; Test swap removal when a vector splat must be adjusted to make it legal.
66 ; Byte splat of element 5 (BE) becomes element 15-5 = 10 (LE)
69 ; Halfword splat of element 6 (BE) becomes element 7-6 = 1 (LE)
72 ; Word splat of element 1 (BE) becomes element 3-1 = 2 (LE)
Dp8-scalar_vector_conversions.ll6 ; to this, there will be a splat corresponding to the shufflevector.
16 %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0
17 …%splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitial…
18 ret <16 x i8> %splat.splat
31 %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0
32 …%splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitiali…
33 ret <8 x i16> %splat.splat
46 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0
47 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali…
48 ret <4 x i32> %splat.splat
[all …]
Dctrloop-fp64.ll37 …%broadcast.splat.i = shufflevector <2 x i64> %broadcast.splatinsert.i, <2 x i64> undef, <2 x i32> …
44 store <2 x i64> %broadcast.splat.i, <2 x i64>* %1, align 8
48 store <2 x i64> %broadcast.splat.i, <2 x i64>* %3, align 8
/external/antlr/antlr-3.4/runtime/Ruby/lib/antlr3/template/
Dparameter.rb9 elsif splat then "*#{ name }"
40 param.splat = options.fetch( :splat, false )
/external/llvm/test/Analysis/CostModel/X86/
Dvshift-lshr-cost.ll118 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
119 %shift = lshr <2 x i64> %a, %splat
131 %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
132 %shift = lshr <4 x i64> %a, %splat
144 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
145 %shift = lshr <4 x i32> %a, %splat
157 %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
158 %shift = lshr <8 x i32> %a, %splat
169 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer
170 %shift = lshr <8 x i16> %a, %splat
[all …]
Dvshift-ashr-cost.ll115 %splat = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
116 %shift = ashr <2 x i64> %a, %splat
127 %splat = shufflevector <4 x i64> %b, <4 x i64> undef, <4 x i32> zeroinitializer
128 %shift = ashr <4 x i64> %a, %splat
140 %splat = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
141 %shift = ashr <4 x i32> %a, %splat
153 %splat = shufflevector <8 x i32> %b, <8 x i32> undef, <8 x i32> zeroinitializer
154 %shift = ashr <8 x i32> %a, %splat
165 %splat = shufflevector <8 x i16> %b, <8 x i16> undef, <8 x i32> zeroinitializer
166 %shift = ashr <8 x i16> %a, %splat
[all …]
/external/llvm/test/Transforms/SLPVectorizer/X86/
Dcommutativity.ll4 ; offers the possibility to splat/broadcast %c and thus make it profitable
16 ; Check that we correctly detect a splat/broadcast by leveraging the
19 ; CHECK-LABEL: @splat
21 define void @splat(i8 %a, i8 %b, i8 %c) {
/external/eigen/Eigen/src/Core/arch/ZVector/
DPacketMath.h265 Packet4f splat;
268 splat.v4f[0] = vec_splat(from.v4f[0], 0);
269 splat.v4f[1] = splat.v4f[0];
272 splat.v4f[0] = vec_splat(from.v4f[0], 1);
273 splat.v4f[1] = splat.v4f[0];
276 splat.v4f[0] = vec_splat(from.v4f[1], 0);
277 splat.v4f[1] = splat.v4f[0];
280 splat.v4f[0] = vec_splat(from.v4f[1], 1);
281 splat.v4f[1] = splat.v4f[0];
284 return splat;

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