1; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s 2; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 | FileCheck %s -check-prefix=CHECK-LE 3 4; The build[csilf] functions simply test the scalar_to_vector handling with 5; direct moves. This corresponds to the "insertelement" instruction. Subsequent 6; to this, there will be a splat corresponding to the shufflevector. 7 8@d = common global double 0.000000e+00, align 8 9 10; Function Attrs: nounwind 11define <16 x i8> @buildc(i8 zeroext %a) { 12entry: 13 %a.addr = alloca i8, align 1 14 store i8 %a, i8* %a.addr, align 1 15 %0 = load i8, i8* %a.addr, align 1 16 %splat.splatinsert = insertelement <16 x i8> undef, i8 %0, i32 0 17 %splat.splat = shufflevector <16 x i8> %splat.splatinsert, <16 x i8> undef, <16 x i32> zeroinitializer 18 ret <16 x i8> %splat.splat 19; CHECK: sldi [[REG1:[0-9]+]], 3, 56 20; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] 21; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 22; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] 23} 24 25; Function Attrs: nounwind 26define <8 x i16> @builds(i16 zeroext %a) { 27entry: 28 %a.addr = alloca i16, align 2 29 store i16 %a, i16* %a.addr, align 2 30 %0 = load i16, i16* %a.addr, align 2 31 %splat.splatinsert = insertelement <8 x i16> undef, i16 %0, i32 0 32 %splat.splat = shufflevector <8 x i16> %splat.splatinsert, <8 x i16> undef, <8 x i32> zeroinitializer 33 ret <8 x i16> %splat.splat 34; CHECK: sldi [[REG1:[0-9]+]], 3, 48 35; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] 36; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 37; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] 38} 39 40; Function Attrs: nounwind 41define <4 x i32> @buildi(i32 zeroext %a) { 42entry: 43 %a.addr = alloca i32, align 4 44 store i32 %a, i32* %a.addr, align 4 45 %0 = load i32, i32* %a.addr, align 4 46 %splat.splatinsert = insertelement <4 x i32> undef, i32 %0, i32 0 47 %splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitializer 48 ret <4 x i32> %splat.splat 49; CHECK: sldi [[REG1:[0-9]+]], 3, 32 50; CHECK: mtvsrd {{[0-9]+}}, [[REG1]] 51; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 52; CHECK-LE: xxswapd {{[0-9]+}}, [[REG1]] 53} 54 55; Function Attrs: nounwind 56define <2 x i64> @buildl(i64 %a) { 57entry: 58 %a.addr = alloca i64, align 8 59 store i64 %a, i64* %a.addr, align 8 60 %0 = load i64, i64* %a.addr, align 8 61 %splat.splatinsert = insertelement <2 x i64> undef, i64 %0, i32 0 62 %splat.splat = shufflevector <2 x i64> %splat.splatinsert, <2 x i64> undef, <2 x i32> zeroinitializer 63 ret <2 x i64> %splat.splat 64; CHECK: mtvsrd {{[0-9]+}}, 3 65; CHECK-LE: mtvsrd [[REG1:[0-9]+]], 3 66; CHECK-LE: xxspltd [[REG1]], [[REG1]], 0 67} 68 69; Function Attrs: nounwind 70define <4 x float> @buildf(float %a) { 71entry: 72 %a.addr = alloca float, align 4 73 store float %a, float* %a.addr, align 4 74 %0 = load float, float* %a.addr, align 4 75 %splat.splatinsert = insertelement <4 x float> undef, float %0, i32 0 76 %splat.splat = shufflevector <4 x float> %splat.splatinsert, <4 x float> undef, <4 x i32> zeroinitializer 77 ret <4 x float> %splat.splat 78; CHECK: xscvdpspn {{[0-9]+}}, 1 79; CHECK-LE: xscvdpspn [[REG1:[0-9]+]], 1 80; CHECK-LE: xxsldwi {{[0-9]+}}, [[REG1]], [[REG1]], 1 81} 82 83; The optimization to remove stack operations from PPCDAGToDAGISel::Select 84; should still trigger for v2f64, producing an lxvdsx. 85; Function Attrs: nounwind 86define <2 x double> @buildd() #0 { 87entry: 88 %0 = load double, double* @d, align 8 89 %splat.splatinsert = insertelement <2 x double> undef, double %0, i32 0 90 %splat.splat = shufflevector <2 x double> %splat.splatinsert, <2 x double> undef, <2 x i32> zeroinitializer 91 ret <2 x double> %splat.splat 92; CHECK: ld [[REG1:[0-9]+]], .LC0@toc@l 93; CHECK: lxvdsx 34, 0, [[REG1]] 94; CHECK-LE: ld [[REG1:[0-9]+]], .LC0@toc@l 95; CHECK-LE: lxvdsx 34, 0, [[REG1]] 96} 97 98; Function Attrs: nounwind 99define signext i8 @getsc0(<16 x i8> %vsc) { 100entry: 101 %vsc.addr = alloca <16 x i8>, align 16 102 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 103 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 104 %vecext = extractelement <16 x i8> %0, i32 0 105 ret i8 %vecext 106; CHECK-LABEL: @getsc0 107; CHECK: mfvsrd 3, 34 108; CHECK: rldicl 3, 3, 8, 56 109; CHECK: extsb 3, 3 110; CHECK-LE-LABEL: @getsc0 111; CHECK-LE: mfvsrd 3, 112; CHECK-LE: clrldi 3, 3, 56 113; CHECK-LE: extsb 3, 3 114} 115 116; Function Attrs: nounwind 117define signext i8 @getsc1(<16 x i8> %vsc) { 118entry: 119 %vsc.addr = alloca <16 x i8>, align 16 120 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 121 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 122 %vecext = extractelement <16 x i8> %0, i32 1 123 ret i8 %vecext 124; CHECK-LABEL: @getsc1 125; CHECK: mfvsrd 3, 34 126; CHECK: rldicl 3, 3, 16, 56 127; CHECK: extsb 3, 3 128; CHECK-LE-LABEL: @getsc1 129; CHECK-LE: mfvsrd 3, 130; CHECK-LE: rldicl 3, 3, 56, 56 131; CHECK-LE: extsb 3, 3 132} 133 134; Function Attrs: nounwind 135define signext i8 @getsc2(<16 x i8> %vsc) { 136entry: 137 %vsc.addr = alloca <16 x i8>, align 16 138 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 139 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 140 %vecext = extractelement <16 x i8> %0, i32 2 141 ret i8 %vecext 142; CHECK-LABEL: @getsc2 143; CHECK: mfvsrd 3, 34 144; CHECK: rldicl 3, 3, 24, 56 145; CHECK: extsb 3, 3 146; CHECK-LE-LABEL: @getsc2 147; CHECK-LE: mfvsrd 3, 148; CHECK-LE: rldicl 3, 3, 48, 56 149; CHECK-LE: extsb 3, 3 150} 151 152; Function Attrs: nounwind 153define signext i8 @getsc3(<16 x i8> %vsc) { 154entry: 155 %vsc.addr = alloca <16 x i8>, align 16 156 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 157 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 158 %vecext = extractelement <16 x i8> %0, i32 3 159 ret i8 %vecext 160; CHECK-LABEL: @getsc3 161; CHECK: mfvsrd 3, 34 162; CHECK: rldicl 3, 3, 32, 56 163; CHECK: extsb 3, 3 164; CHECK-LE-LABEL: @getsc3 165; CHECK-LE: mfvsrd 3, 166; CHECK-LE: rldicl 3, 3, 40, 56 167; CHECK-LE: extsb 3, 3 168} 169 170; Function Attrs: nounwind 171define signext i8 @getsc4(<16 x i8> %vsc) { 172entry: 173 %vsc.addr = alloca <16 x i8>, align 16 174 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 175 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 176 %vecext = extractelement <16 x i8> %0, i32 4 177 ret i8 %vecext 178; CHECK-LABEL: @getsc4 179; CHECK: mfvsrd 3, 34 180; CHECK: rldicl 3, 3, 40, 56 181; CHECK: extsb 3, 3 182; CHECK-LE-LABEL: @getsc4 183; CHECK-LE: mfvsrd 3, 184; CHECK-LE: rldicl 3, 3, 32, 56 185; CHECK-LE: extsb 3, 3 186} 187 188; Function Attrs: nounwind 189define signext i8 @getsc5(<16 x i8> %vsc) { 190entry: 191 %vsc.addr = alloca <16 x i8>, align 16 192 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 193 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 194 %vecext = extractelement <16 x i8> %0, i32 5 195 ret i8 %vecext 196; CHECK-LABEL: @getsc5 197; CHECK: mfvsrd 3, 34 198; CHECK: rldicl 3, 3, 48, 56 199; CHECK: extsb 3, 3 200; CHECK-LE-LABEL: @getsc5 201; CHECK-LE: mfvsrd 3, 202; CHECK-LE: rldicl 3, 3, 24, 56 203; CHECK-LE: extsb 3, 3 204} 205 206; Function Attrs: nounwind 207define signext i8 @getsc6(<16 x i8> %vsc) { 208entry: 209 %vsc.addr = alloca <16 x i8>, align 16 210 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 211 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 212 %vecext = extractelement <16 x i8> %0, i32 6 213 ret i8 %vecext 214; CHECK-LABEL: @getsc6 215; CHECK: mfvsrd 3, 34 216; CHECK: rldicl 3, 3, 56, 56 217; CHECK: extsb 3, 3 218; CHECK-LE-LABEL: @getsc6 219; CHECK-LE: mfvsrd 3, 220; CHECK-LE: rldicl 3, 3, 16, 56 221; CHECK-LE: extsb 3, 3 222} 223 224; Function Attrs: nounwind 225define signext i8 @getsc7(<16 x i8> %vsc) { 226entry: 227 %vsc.addr = alloca <16 x i8>, align 16 228 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 229 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 230 %vecext = extractelement <16 x i8> %0, i32 7 231 ret i8 %vecext 232; CHECK-LABEL: @getsc7 233; CHECK: mfvsrd 3, 34 234; CHECK: clrldi 3, 3, 56 235; CHECK: extsb 3, 3 236; CHECK-LE-LABEL: @getsc7 237; CHECK-LE: mfvsrd 3, 238; CHECK-LE: rldicl 3, 3, 8, 56 239; CHECK-LE: extsb 3, 3 240} 241 242; Function Attrs: nounwind 243define signext i8 @getsc8(<16 x i8> %vsc) { 244entry: 245 %vsc.addr = alloca <16 x i8>, align 16 246 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 247 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 248 %vecext = extractelement <16 x i8> %0, i32 8 249 ret i8 %vecext 250; CHECK-LABEL: @getsc8 251; CHECK: mfvsrd 3, 252; CHECK: rldicl 3, 3, 8, 56 253; CHECK: extsb 3, 3 254; CHECK-LE-LABEL: @getsc8 255; CHECK-LE: mfvsrd 3, 34 256; CHECK-LE: clrldi 3, 3, 56 257; CHECK-LE: extsb 3, 3 258} 259 260; Function Attrs: nounwind 261define signext i8 @getsc9(<16 x i8> %vsc) { 262entry: 263 %vsc.addr = alloca <16 x i8>, align 16 264 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 265 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 266 %vecext = extractelement <16 x i8> %0, i32 9 267 ret i8 %vecext 268; CHECK-LABEL: @getsc9 269; CHECK: mfvsrd 3, 270; CHECK: rldicl 3, 3, 16, 56 271; CHECK: extsb 3, 3 272; CHECK-LE-LABEL: @getsc9 273; CHECK-LE: mfvsrd 3, 34 274; CHECK-LE: rldicl 3, 3, 56, 56 275; CHECK-LE: extsb 3, 3 276} 277 278; Function Attrs: nounwind 279define signext i8 @getsc10(<16 x i8> %vsc) { 280entry: 281 %vsc.addr = alloca <16 x i8>, align 16 282 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 283 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 284 %vecext = extractelement <16 x i8> %0, i32 10 285 ret i8 %vecext 286; CHECK-LABEL: @getsc10 287; CHECK: mfvsrd 3, 288; CHECK: rldicl 3, 3, 24, 56 289; CHECK: extsb 3, 3 290; CHECK-LE-LABEL: @getsc10 291; CHECK-LE: mfvsrd 3, 34 292; CHECK-LE: rldicl 3, 3, 48, 56 293; CHECK-LE: extsb 3, 3 294} 295 296; Function Attrs: nounwind 297define signext i8 @getsc11(<16 x i8> %vsc) { 298entry: 299 %vsc.addr = alloca <16 x i8>, align 16 300 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 301 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 302 %vecext = extractelement <16 x i8> %0, i32 11 303 ret i8 %vecext 304; CHECK-LABEL: @getsc11 305; CHECK: mfvsrd 3, 306; CHECK: rldicl 3, 3, 32, 56 307; CHECK: extsb 3, 3 308; CHECK-LE-LABEL: @getsc11 309; CHECK-LE: mfvsrd 3, 34 310; CHECK-LE: rldicl 3, 3, 40, 56 311; CHECK-LE: extsb 3, 3 312} 313 314; Function Attrs: nounwind 315define signext i8 @getsc12(<16 x i8> %vsc) { 316entry: 317 %vsc.addr = alloca <16 x i8>, align 16 318 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 319 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 320 %vecext = extractelement <16 x i8> %0, i32 12 321 ret i8 %vecext 322; CHECK-LABEL: @getsc12 323; CHECK: mfvsrd 3, 324; CHECK: rldicl 3, 3, 40, 56 325; CHECK: extsb 3, 3 326; CHECK-LE-LABEL: @getsc12 327; CHECK-LE: mfvsrd 3, 34 328; CHECK-LE: rldicl 3, 3, 32, 56 329; CHECK-LE: extsb 3, 3 330} 331 332; Function Attrs: nounwind 333define signext i8 @getsc13(<16 x i8> %vsc) { 334entry: 335 %vsc.addr = alloca <16 x i8>, align 16 336 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 337 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 338 %vecext = extractelement <16 x i8> %0, i32 13 339 ret i8 %vecext 340; CHECK-LABEL: @getsc13 341; CHECK: mfvsrd 3, 342; CHECK: rldicl 3, 3, 48, 56 343; CHECK: extsb 3, 3 344; CHECK-LE-LABEL: @getsc13 345; CHECK-LE: mfvsrd 3, 34 346; CHECK-LE: rldicl 3, 3, 24, 56 347; CHECK-LE: extsb 3, 3 348} 349 350; Function Attrs: nounwind 351define signext i8 @getsc14(<16 x i8> %vsc) { 352entry: 353 %vsc.addr = alloca <16 x i8>, align 16 354 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 355 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 356 %vecext = extractelement <16 x i8> %0, i32 14 357 ret i8 %vecext 358; CHECK-LABEL: @getsc14 359; CHECK: mfvsrd 3, 360; CHECK: rldicl 3, 3, 56, 56 361; CHECK: extsb 3, 3 362; CHECK-LE-LABEL: @getsc14 363; CHECK-LE: mfvsrd 3, 34 364; CHECK-LE: rldicl 3, 3, 16, 56 365; CHECK-LE: extsb 3, 3 366} 367 368; Function Attrs: nounwind 369define signext i8 @getsc15(<16 x i8> %vsc) { 370entry: 371 %vsc.addr = alloca <16 x i8>, align 16 372 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 373 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 374 %vecext = extractelement <16 x i8> %0, i32 15 375 ret i8 %vecext 376; CHECK-LABEL: @getsc15 377; CHECK: mfvsrd 3, 378; CHECK: extsb 3, 3 379; CHECK-LE-LABEL: @getsc15 380; CHECK-LE: mfvsrd 3, 34 381; CHECK-LE: rldicl 3, 3, 8, 56 382; CHECK-LE: extsb 3, 3 383} 384 385; Function Attrs: nounwind 386define zeroext i8 @getuc0(<16 x i8> %vuc) { 387entry: 388 %vuc.addr = alloca <16 x i8>, align 16 389 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 390 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 391 %vecext = extractelement <16 x i8> %0, i32 0 392 ret i8 %vecext 393; CHECK-LABEL: @getuc0 394; CHECK: mfvsrd 3, 34 395; CHECK: rldicl 3, 3, 8, 56 396; CHECK: clrldi 3, 3, 56 397; CHECK-LE-LABEL: @getuc0 398; CHECK-LE: mfvsrd 3, 399; CHECK-LE: clrldi 3, 3, 56 400} 401 402; Function Attrs: nounwind 403define zeroext i8 @getuc1(<16 x i8> %vuc) { 404entry: 405 %vuc.addr = alloca <16 x i8>, align 16 406 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 407 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 408 %vecext = extractelement <16 x i8> %0, i32 1 409 ret i8 %vecext 410; CHECK-LABEL: @getuc1 411; CHECK: mfvsrd 3, 34 412; CHECK: rldicl 3, 3, 16, 56 413; CHECK: clrldi 3, 3, 56 414; CHECK-LE-LABEL: @getuc1 415; CHECK-LE: mfvsrd 3, 416; CHECK-LE: rldicl 3, 3, 56, 56 417; CHECK-LE: clrldi 3, 3, 56 418} 419 420; Function Attrs: nounwind 421define zeroext i8 @getuc2(<16 x i8> %vuc) { 422entry: 423 %vuc.addr = alloca <16 x i8>, align 16 424 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 425 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 426 %vecext = extractelement <16 x i8> %0, i32 2 427 ret i8 %vecext 428; CHECK-LABEL: @getuc2 429; CHECK: mfvsrd 3, 34 430; CHECK: rldicl 3, 3, 24, 56 431; CHECK: clrldi 3, 3, 56 432; CHECK-LE-LABEL: @getuc2 433; CHECK-LE: mfvsrd 3, 434; CHECK-LE: rldicl 3, 3, 48, 56 435; CHECK-LE: clrldi 3, 3, 56 436} 437 438; Function Attrs: nounwind 439define zeroext i8 @getuc3(<16 x i8> %vuc) { 440entry: 441 %vuc.addr = alloca <16 x i8>, align 16 442 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 443 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 444 %vecext = extractelement <16 x i8> %0, i32 3 445 ret i8 %vecext 446; CHECK-LABEL: @getuc3 447; CHECK: mfvsrd 3, 34 448; CHECK: rldicl 3, 3, 32, 56 449; CHECK: clrldi 3, 3, 56 450; CHECK-LE-LABEL: @getuc3 451; CHECK-LE: mfvsrd 3, 452; CHECK-LE: rldicl 3, 3, 40, 56 453; CHECK-LE: clrldi 3, 3, 56 454} 455 456; Function Attrs: nounwind 457define zeroext i8 @getuc4(<16 x i8> %vuc) { 458entry: 459 %vuc.addr = alloca <16 x i8>, align 16 460 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 461 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 462 %vecext = extractelement <16 x i8> %0, i32 4 463 ret i8 %vecext 464; CHECK-LABEL: @getuc4 465; CHECK: mfvsrd 3, 34 466; CHECK: rldicl 3, 3, 40, 56 467; CHECK: clrldi 3, 3, 56 468; CHECK-LE-LABEL: @getuc4 469; CHECK-LE: mfvsrd 3, 470; CHECK-LE: rldicl 3, 3, 32, 56 471; CHECK-LE: clrldi 3, 3, 56 472} 473 474; Function Attrs: nounwind 475define zeroext i8 @getuc5(<16 x i8> %vuc) { 476entry: 477 %vuc.addr = alloca <16 x i8>, align 16 478 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 479 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 480 %vecext = extractelement <16 x i8> %0, i32 5 481 ret i8 %vecext 482; CHECK-LABEL: @getuc5 483; CHECK: mfvsrd 3, 34 484; CHECK: rldicl 3, 3, 48, 56 485; CHECK: clrldi 3, 3, 56 486; CHECK-LE-LABEL: @getuc5 487; CHECK-LE: mfvsrd 3, 488; CHECK-LE: rldicl 3, 3, 24, 56 489; CHECK-LE: clrldi 3, 3, 56 490} 491 492; Function Attrs: nounwind 493define zeroext i8 @getuc6(<16 x i8> %vuc) { 494entry: 495 %vuc.addr = alloca <16 x i8>, align 16 496 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 497 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 498 %vecext = extractelement <16 x i8> %0, i32 6 499 ret i8 %vecext 500; CHECK-LABEL: @getuc6 501; CHECK: mfvsrd 3, 34 502; CHECK: rldicl 3, 3, 56, 56 503; CHECK: clrldi 3, 3, 56 504; CHECK-LE-LABEL: @getuc6 505; CHECK-LE: mfvsrd 3, 506; CHECK-LE: rldicl 3, 3, 16, 56 507; CHECK-LE: clrldi 3, 3, 56 508} 509 510; Function Attrs: nounwind 511define zeroext i8 @getuc7(<16 x i8> %vuc) { 512entry: 513 %vuc.addr = alloca <16 x i8>, align 16 514 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 515 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 516 %vecext = extractelement <16 x i8> %0, i32 7 517 ret i8 %vecext 518; CHECK-LABEL: @getuc7 519; CHECK: mfvsrd 3, 34 520; CHECK: clrldi 3, 3, 56 521; CHECK-LE-LABEL: @getuc7 522; CHECK-LE: mfvsrd 3, 523; CHECK-LE: rldicl 3, 3, 8, 56 524; CHECK-LE: clrldi 3, 3, 56 525} 526 527; Function Attrs: nounwind 528define zeroext i8 @getuc8(<16 x i8> %vuc) { 529entry: 530 %vuc.addr = alloca <16 x i8>, align 16 531 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 532 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 533 %vecext = extractelement <16 x i8> %0, i32 8 534 ret i8 %vecext 535; CHECK-LABEL: @getuc8 536; CHECK: mfvsrd 3, 537; CHECK: rldicl 3, 3, 8, 56 538; CHECK: clrldi 3, 3, 56 539; CHECK-LE-LABEL: @getuc8 540; CHECK-LE: mfvsrd 3, 34 541; CHECK-LE: clrldi 3, 3, 56 542} 543 544; Function Attrs: nounwind 545define zeroext i8 @getuc9(<16 x i8> %vuc) { 546entry: 547 %vuc.addr = alloca <16 x i8>, align 16 548 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 549 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 550 %vecext = extractelement <16 x i8> %0, i32 9 551 ret i8 %vecext 552; CHECK-LABEL: @getuc9 553; CHECK: mfvsrd 3, 554; CHECK: rldicl 3, 3, 16, 56 555; CHECK: clrldi 3, 3, 56 556; CHECK-LE-LABEL: @getuc9 557; CHECK-LE: mfvsrd 3, 34 558; CHECK-LE: rldicl 3, 3, 56, 56 559; CHECK-LE: clrldi 3, 3, 56 560} 561 562; Function Attrs: nounwind 563define zeroext i8 @getuc10(<16 x i8> %vuc) { 564entry: 565 %vuc.addr = alloca <16 x i8>, align 16 566 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 567 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 568 %vecext = extractelement <16 x i8> %0, i32 10 569 ret i8 %vecext 570; CHECK-LABEL: @getuc10 571; CHECK: mfvsrd 3, 572; CHECK: rldicl 3, 3, 24, 56 573; CHECK: clrldi 3, 3, 56 574; CHECK-LE-LABEL: @getuc10 575; CHECK-LE: mfvsrd 3, 34 576; CHECK-LE: rldicl 3, 3, 48, 56 577; CHECK-LE: clrldi 3, 3, 56 578} 579 580; Function Attrs: nounwind 581define zeroext i8 @getuc11(<16 x i8> %vuc) { 582entry: 583 %vuc.addr = alloca <16 x i8>, align 16 584 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 585 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 586 %vecext = extractelement <16 x i8> %0, i32 11 587 ret i8 %vecext 588; CHECK-LABEL: @getuc11 589; CHECK: mfvsrd 3, 590; CHECK: rldicl 3, 3, 32, 56 591; CHECK: clrldi 3, 3, 56 592; CHECK-LE-LABEL: @getuc11 593; CHECK-LE: mfvsrd 3, 34 594; CHECK-LE: rldicl 3, 3, 40, 56 595; CHECK-LE: clrldi 3, 3, 56 596} 597 598; Function Attrs: nounwind 599define zeroext i8 @getuc12(<16 x i8> %vuc) { 600entry: 601 %vuc.addr = alloca <16 x i8>, align 16 602 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 603 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 604 %vecext = extractelement <16 x i8> %0, i32 12 605 ret i8 %vecext 606; CHECK-LABEL: @getuc12 607; CHECK: mfvsrd 3, 608; CHECK: rldicl 3, 3, 40, 56 609; CHECK: clrldi 3, 3, 56 610; CHECK-LE-LABEL: @getuc12 611; CHECK-LE: mfvsrd 3, 34 612; CHECK-LE: rldicl 3, 3, 32, 56 613; CHECK-LE: clrldi 3, 3, 56 614} 615 616; Function Attrs: nounwind 617define zeroext i8 @getuc13(<16 x i8> %vuc) { 618entry: 619 %vuc.addr = alloca <16 x i8>, align 16 620 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 621 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 622 %vecext = extractelement <16 x i8> %0, i32 13 623 ret i8 %vecext 624; CHECK-LABEL: @getuc13 625; CHECK: mfvsrd 3, 626; CHECK: rldicl 3, 3, 48, 56 627; CHECK: clrldi 3, 3, 56 628; CHECK-LE-LABEL: @getuc13 629; CHECK-LE: mfvsrd 3, 34 630; CHECK-LE: rldicl 3, 3, 24, 56 631; CHECK-LE: clrldi 3, 3, 56 632} 633 634; Function Attrs: nounwind 635define zeroext i8 @getuc14(<16 x i8> %vuc) { 636entry: 637 %vuc.addr = alloca <16 x i8>, align 16 638 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 639 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 640 %vecext = extractelement <16 x i8> %0, i32 14 641 ret i8 %vecext 642; CHECK-LABEL: @getuc14 643; CHECK: mfvsrd 3, 644; CHECK: rldicl 3, 3, 56, 56 645; CHECK: clrldi 3, 3, 56 646; CHECK-LE-LABEL: @getuc14 647; CHECK-LE: mfvsrd 3, 34 648; CHECK-LE: rldicl 3, 3, 16, 56 649; CHECK-LE: clrldi 3, 3, 56 650} 651 652; Function Attrs: nounwind 653define zeroext i8 @getuc15(<16 x i8> %vuc) { 654entry: 655 %vuc.addr = alloca <16 x i8>, align 16 656 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 657 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 658 %vecext = extractelement <16 x i8> %0, i32 15 659 ret i8 %vecext 660; CHECK-LABEL: @getuc15 661; CHECK: mfvsrd 3, 662; CHECK: clrldi 3, 3, 56 663; CHECK-LE-LABEL: @getuc15 664; CHECK-LE: mfvsrd 3, 34 665; CHECK-LE: rldicl 3, 3, 8, 56 666; CHECK-LE: clrldi 3, 3, 56 667} 668 669; Function Attrs: nounwind 670define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) { 671entry: 672 %vsc.addr = alloca <16 x i8>, align 16 673 %i.addr = alloca i32, align 4 674 store <16 x i8> %vsc, <16 x i8>* %vsc.addr, align 16 675 store i32 %i, i32* %i.addr, align 4 676 %0 = load <16 x i8>, <16 x i8>* %vsc.addr, align 16 677 %1 = load i32, i32* %i.addr, align 4 678 %vecext = extractelement <16 x i8> %0, i32 %1 679 ret i8 %vecext 680; CHECK-LABEL: @getvelsc 681; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 682; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] 683; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 684; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 685; CHECK-DAG: li [[IMM7:[0-9]+]], 7 686; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] 687; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 688; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 689; CHECK-DAG: extsb 3, 3 690; CHECK-LE-LABEL: @getvelsc 691; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 692; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] 693; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] 694; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 695; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 696; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 697; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] 698; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 699; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 700; CHECK-DAG-LE: extsb 3, 3 701} 702 703; Function Attrs: nounwind 704define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) { 705entry: 706 %vuc.addr = alloca <16 x i8>, align 16 707 %i.addr = alloca i32, align 4 708 store <16 x i8> %vuc, <16 x i8>* %vuc.addr, align 16 709 store i32 %i, i32* %i.addr, align 4 710 %0 = load <16 x i8>, <16 x i8>* %vuc.addr, align 16 711 %1 = load i32, i32* %i.addr, align 4 712 %vecext = extractelement <16 x i8> %0, i32 %1 713 ret i8 %vecext 714; CHECK-LABEL: @getveluc 715; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 8 716; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[ANDI]] 717; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 718; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 719; CHECK-DAG: li [[IMM7:[0-9]+]], 7 720; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM7]] 721; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 3 722; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 723; CHECK-DAG: clrldi 3, 3, 56 724; CHECK-LE-LABEL: @getveluc 725; CHECK-DAG-LE: li [[IMM8:[0-9]+]], 8 726; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM8]] 727; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[ANDC]] 728; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 729; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 730; CHECK-DAG-LE: li [[IMM7:[0-9]+]], 7 731; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM7]] 732; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 3 733; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 734; CHECK-DAG-LE: clrldi 3, 3, 56 735} 736 737; Function Attrs: nounwind 738define signext i16 @getss0(<8 x i16> %vss) { 739entry: 740 %vss.addr = alloca <8 x i16>, align 16 741 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 742 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 743 %vecext = extractelement <8 x i16> %0, i32 0 744 ret i16 %vecext 745; CHECK-LABEL: @getss0 746; CHECK: mfvsrd 3, 34 747; CHECK: rldicl 3, 3, 16, 48 748; CHECK: extsh 3, 3 749; CHECK-LE-LABEL: @getss0 750; CHECK-LE: mfvsrd 3, 751; CHECK-LE: clrldi 3, 3, 48 752; CHECK-LE: extsh 3, 3 753} 754 755; Function Attrs: nounwind 756define signext i16 @getss1(<8 x i16> %vss) { 757entry: 758 %vss.addr = alloca <8 x i16>, align 16 759 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 760 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 761 %vecext = extractelement <8 x i16> %0, i32 1 762 ret i16 %vecext 763; CHECK-LABEL: @getss1 764; CHECK: mfvsrd 3, 34 765; CHECK: rldicl 3, 3, 32, 48 766; CHECK: extsh 3, 3 767; CHECK-LE-LABEL: @getss1 768; CHECK-LE: mfvsrd 3, 769; CHECK-LE: rldicl 3, 3, 48, 48 770; CHECK-LE: extsh 3, 3 771} 772 773; Function Attrs: nounwind 774define signext i16 @getss2(<8 x i16> %vss) { 775entry: 776 %vss.addr = alloca <8 x i16>, align 16 777 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 778 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 779 %vecext = extractelement <8 x i16> %0, i32 2 780 ret i16 %vecext 781; CHECK-LABEL: @getss2 782; CHECK: mfvsrd 3, 34 783; CHECK: rldicl 3, 3, 48, 48 784; CHECK: extsh 3, 3 785; CHECK-LE-LABEL: @getss2 786; CHECK-LE: mfvsrd 3, 787; CHECK-LE: rldicl 3, 3, 32, 48 788; CHECK-LE: extsh 3, 3 789} 790 791; Function Attrs: nounwind 792define signext i16 @getss3(<8 x i16> %vss) { 793entry: 794 %vss.addr = alloca <8 x i16>, align 16 795 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 796 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 797 %vecext = extractelement <8 x i16> %0, i32 3 798 ret i16 %vecext 799; CHECK-LABEL: @getss3 800; CHECK: mfvsrd 3, 34 801; CHECK: clrldi 3, 3, 48 802; CHECK: extsh 3, 3 803; CHECK-LE-LABEL: @getss3 804; CHECK-LE: mfvsrd 3, 805; CHECK-LE: rldicl 3, 3, 16, 48 806; CHECK-LE: extsh 3, 3 807} 808 809; Function Attrs: nounwind 810define signext i16 @getss4(<8 x i16> %vss) { 811entry: 812 %vss.addr = alloca <8 x i16>, align 16 813 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 814 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 815 %vecext = extractelement <8 x i16> %0, i32 4 816 ret i16 %vecext 817; CHECK-LABEL: @getss4 818; CHECK: mfvsrd 3, 819; CHECK: rldicl 3, 3, 16, 48 820; CHECK: extsh 3, 3 821; CHECK-LE-LABEL: @getss4 822; CHECK-LE: mfvsrd 3, 34 823; CHECK-LE: clrldi 3, 3, 48 824; CHECK-LE: extsh 3, 3 825} 826 827; Function Attrs: nounwind 828define signext i16 @getss5(<8 x i16> %vss) { 829entry: 830 %vss.addr = alloca <8 x i16>, align 16 831 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 832 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 833 %vecext = extractelement <8 x i16> %0, i32 5 834 ret i16 %vecext 835; CHECK-LABEL: @getss5 836; CHECK: mfvsrd 3, 837; CHECK: rldicl 3, 3, 32, 48 838; CHECK: extsh 3, 3 839; CHECK-LE-LABEL: @getss5 840; CHECK-LE: mfvsrd 3, 34 841; CHECK-LE: rldicl 3, 3, 48, 48 842; CHECK-LE: extsh 3, 3 843} 844 845; Function Attrs: nounwind 846define signext i16 @getss6(<8 x i16> %vss) { 847entry: 848 %vss.addr = alloca <8 x i16>, align 16 849 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 850 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 851 %vecext = extractelement <8 x i16> %0, i32 6 852 ret i16 %vecext 853; CHECK-LABEL: @getss6 854; CHECK: mfvsrd 3, 855; CHECK: rldicl 3, 3, 48, 48 856; CHECK: extsh 3, 3 857; CHECK-LE-LABEL: @getss6 858; CHECK-LE: mfvsrd 3, 34 859; CHECK-LE: rldicl 3, 3, 32, 48 860; CHECK-LE: extsh 3, 3 861} 862 863; Function Attrs: nounwind 864define signext i16 @getss7(<8 x i16> %vss) { 865entry: 866 %vss.addr = alloca <8 x i16>, align 16 867 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 868 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 869 %vecext = extractelement <8 x i16> %0, i32 7 870 ret i16 %vecext 871; CHECK-LABEL: @getss7 872; CHECK: mfvsrd 3, 873; CHECK: extsh 3, 3 874; CHECK-LE-LABEL: @getss7 875; CHECK-LE: mfvsrd 3, 34 876; CHECK-LE: rldicl 3, 3, 16, 48 877; CHECK-LE: extsh 3, 3 878} 879 880; Function Attrs: nounwind 881define zeroext i16 @getus0(<8 x i16> %vus) { 882entry: 883 %vus.addr = alloca <8 x i16>, align 16 884 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 885 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 886 %vecext = extractelement <8 x i16> %0, i32 0 887 ret i16 %vecext 888; CHECK-LABEL: @getus0 889; CHECK: mfvsrd 3, 34 890; CHECK: rldicl 3, 3, 16, 48 891; CHECK: clrldi 3, 3, 48 892; CHECK-LE-LABEL: @getus0 893; CHECK-LE: mfvsrd 3, 894; CHECK-LE: clrldi 3, 3, 48 895} 896 897; Function Attrs: nounwind 898define zeroext i16 @getus1(<8 x i16> %vus) { 899entry: 900 %vus.addr = alloca <8 x i16>, align 16 901 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 902 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 903 %vecext = extractelement <8 x i16> %0, i32 1 904 ret i16 %vecext 905; CHECK-LABEL: @getus1 906; CHECK: mfvsrd 3, 34 907; CHECK: rldicl 3, 3, 32, 48 908; CHECK: clrldi 3, 3, 48 909; CHECK-LE-LABEL: @getus1 910; CHECK-LE: mfvsrd 3, 911; CHECK-LE: rldicl 3, 3, 48, 48 912; CHECK-LE: clrldi 3, 3, 48 913} 914 915; Function Attrs: nounwind 916define zeroext i16 @getus2(<8 x i16> %vus) { 917entry: 918 %vus.addr = alloca <8 x i16>, align 16 919 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 920 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 921 %vecext = extractelement <8 x i16> %0, i32 2 922 ret i16 %vecext 923; CHECK-LABEL: @getus2 924; CHECK: mfvsrd 3, 34 925; CHECK: rldicl 3, 3, 48, 48 926; CHECK: clrldi 3, 3, 48 927; CHECK-LE-LABEL: @getus2 928; CHECK-LE: mfvsrd 3, 929; CHECK-LE: rldicl 3, 3, 32, 48 930; CHECK-LE: clrldi 3, 3, 48 931} 932 933; Function Attrs: nounwind 934define zeroext i16 @getus3(<8 x i16> %vus) { 935entry: 936 %vus.addr = alloca <8 x i16>, align 16 937 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 938 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 939 %vecext = extractelement <8 x i16> %0, i32 3 940 ret i16 %vecext 941; CHECK-LABEL: @getus3 942; CHECK: mfvsrd 3, 34 943; CHECK: clrldi 3, 3, 48 944; CHECK-LE-LABEL: @getus3 945; CHECK-LE: mfvsrd 3, 946; CHECK-LE: rldicl 3, 3, 16, 48 947; CHECK-LE: clrldi 3, 3, 48 948} 949 950; Function Attrs: nounwind 951define zeroext i16 @getus4(<8 x i16> %vus) { 952entry: 953 %vus.addr = alloca <8 x i16>, align 16 954 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 955 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 956 %vecext = extractelement <8 x i16> %0, i32 4 957 ret i16 %vecext 958; CHECK-LABEL: @getus4 959; CHECK: mfvsrd 3, 960; CHECK: rldicl 3, 3, 16, 48 961; CHECK: clrldi 3, 3, 48 962; CHECK-LE-LABEL: @getus4 963; CHECK-LE: mfvsrd 3, 34 964; CHECK-LE: clrldi 3, 3, 48 965} 966 967; Function Attrs: nounwind 968define zeroext i16 @getus5(<8 x i16> %vus) { 969entry: 970 %vus.addr = alloca <8 x i16>, align 16 971 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 972 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 973 %vecext = extractelement <8 x i16> %0, i32 5 974 ret i16 %vecext 975; CHECK-LABEL: @getus5 976; CHECK: mfvsrd 3, 977; CHECK: rldicl 3, 3, 32, 48 978; CHECK: clrldi 3, 3, 48 979; CHECK-LE-LABEL: @getus5 980; CHECK-LE: mfvsrd 3, 34 981; CHECK-LE: rldicl 3, 3, 48, 48 982; CHECK-LE: clrldi 3, 3, 48 983} 984 985; Function Attrs: nounwind 986define zeroext i16 @getus6(<8 x i16> %vus) { 987entry: 988 %vus.addr = alloca <8 x i16>, align 16 989 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 990 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 991 %vecext = extractelement <8 x i16> %0, i32 6 992 ret i16 %vecext 993; CHECK-LABEL: @getus6 994; CHECK: mfvsrd 3, 995; CHECK: rldicl 3, 3, 48, 48 996; CHECK: clrldi 3, 3, 48 997; CHECK-LE-LABEL: @getus6 998; CHECK-LE: mfvsrd 3, 34 999; CHECK-LE: rldicl 3, 3, 32, 48 1000; CHECK-LE: clrldi 3, 3, 48 1001} 1002 1003; Function Attrs: nounwind 1004define zeroext i16 @getus7(<8 x i16> %vus) { 1005entry: 1006 %vus.addr = alloca <8 x i16>, align 16 1007 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 1008 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 1009 %vecext = extractelement <8 x i16> %0, i32 7 1010 ret i16 %vecext 1011; CHECK-LABEL: @getus7 1012; CHECK: mfvsrd 3, 1013; CHECK: clrldi 3, 3, 48 1014; CHECK-LE-LABEL: @getus7 1015; CHECK-LE: mfvsrd 3, 34 1016; CHECK-LE: rldicl 3, 3, 16, 48 1017; CHECK-LE: clrldi 3, 3, 48 1018} 1019 1020; Function Attrs: nounwind 1021define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) { 1022entry: 1023 %vss.addr = alloca <8 x i16>, align 16 1024 %i.addr = alloca i32, align 4 1025 store <8 x i16> %vss, <8 x i16>* %vss.addr, align 16 1026 store i32 %i, i32* %i.addr, align 4 1027 %0 = load <8 x i16>, <8 x i16>* %vss.addr, align 16 1028 %1 = load i32, i32* %i.addr, align 4 1029 %vecext = extractelement <8 x i16> %0, i32 %1 1030 ret i16 %vecext 1031; CHECK-LABEL: @getvelss 1032; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 1033; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 1034; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1035; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1036; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 1037; CHECK-DAG: li [[IMM3:[0-9]+]], 3 1038; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] 1039; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 1040; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 1041; CHECK-DAG: extsh 3, 3 1042; CHECK-LE-LABEL: @getvelss 1043; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 1044; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] 1045; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 1046; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1047; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1048; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 1049; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 1050; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] 1051; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 1052; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 1053; CHECK-DAG-LE: extsh 3, 3 1054} 1055 1056; Function Attrs: nounwind 1057define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) { 1058entry: 1059 %vus.addr = alloca <8 x i16>, align 16 1060 %i.addr = alloca i32, align 4 1061 store <8 x i16> %vus, <8 x i16>* %vus.addr, align 16 1062 store i32 %i, i32* %i.addr, align 4 1063 %0 = load <8 x i16>, <8 x i16>* %vus.addr, align 16 1064 %1 = load i32, i32* %i.addr, align 4 1065 %vecext = extractelement <8 x i16> %0, i32 %1 1066 ret i16 %vecext 1067; CHECK-LABEL: @getvelus 1068; CHECK-DAG: andi. [[ANDI:[0-9]+]], {{[0-9]+}}, 4 1069; CHECK-DAG: sldi [[MUL2:[0-9]+]], [[ANDI]], 1 1070; CHECK-DAG: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1071; CHECK-DAG: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1072; CHECK-DAG: mfvsrd [[MOV:[0-9]+]], 1073; CHECK-DAG: li [[IMM3:[0-9]+]], 3 1074; CHECK-DAG: andc [[ANDC:[0-9]+]], [[IMM3]] 1075; CHECK-DAG: sldi [[SHL:[0-9]+]], [[ANDC]], 4 1076; CHECK-DAG: srd 3, [[MOV]], [[SHL]] 1077; CHECK-DAG: clrldi 3, 3, 48 1078; CHECK-LE-LABEL: @getvelus 1079; CHECK-DAG-LE: li [[IMM4:[0-9]+]], 4 1080; CHECK-DAG-LE: andc [[ANDC:[0-9]+]], [[IMM4]] 1081; CHECK-DAG-LE: sldi [[MUL2:[0-9]+]], [[ANDC]], 1 1082; CHECK-DAG-LE: lvsl [[SHMSK:[0-9]+]], 0, [[MUL2]] 1083; CHECK-DAG-LE: vperm [[PERMD:[0-9]+]], {{[0-9]+}}, {{[0-9]+}}, [[SHMSK]] 1084; CHECK-DAG-LE: mfvsrd [[MOV:[0-9]+]], 1085; CHECK-DAG-LE: li [[IMM3:[0-9]+]], 3 1086; CHECK-DAG-LE: and [[AND:[0-9]+]], [[IMM3]] 1087; CHECK-DAG-LE: sldi [[SHL:[0-9]+]], [[AND]], 4 1088; CHECK-DAG-LE: srd 3, [[MOV]], [[SHL]] 1089; CHECK-DAG-LE: clrldi 3, 3, 48 1090} 1091 1092; Function Attrs: nounwind 1093define signext i32 @getsi0(<4 x i32> %vsi) { 1094entry: 1095 %vsi.addr = alloca <4 x i32>, align 16 1096 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1097 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1098 %vecext = extractelement <4 x i32> %0, i32 0 1099 ret i32 %vecext 1100; CHECK-LABEL: @getsi0 1101; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1102; CHECK: mfvsrwz 3, [[SHL]] 1103; CHECK: extsw 3, 3 1104; CHECK-LE-LABEL: @getsi0 1105; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1106; CHECK-LE: mfvsrwz 3, [[SHL]] 1107; CHECK-LE: extsw 3, 3 1108} 1109 1110; Function Attrs: nounwind 1111define signext i32 @getsi1(<4 x i32> %vsi) { 1112entry: 1113 %vsi.addr = alloca <4 x i32>, align 16 1114 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1115 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1116 %vecext = extractelement <4 x i32> %0, i32 1 1117 ret i32 %vecext 1118; CHECK-LABEL: @getsi1 1119; CHECK: mfvsrwz 3, 34 1120; CHECK: extsw 3, 3 1121; CHECK-LE-LABEL: @getsi1 1122; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1123; CHECK-LE: mfvsrwz 3, [[SHL]] 1124; CHECK-LE: extsw 3, 3 1125} 1126 1127; Function Attrs: nounwind 1128define signext i32 @getsi2(<4 x i32> %vsi) { 1129entry: 1130 %vsi.addr = alloca <4 x i32>, align 16 1131 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1132 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1133 %vecext = extractelement <4 x i32> %0, i32 2 1134 ret i32 %vecext 1135; CHECK-LABEL: @getsi2 1136; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1137; CHECK: mfvsrwz 3, [[SHL]] 1138; CHECK: extsw 3, 3 1139; CHECK-LE-LABEL: @getsi2 1140; CHECK-LE: mfvsrwz 3, 34 1141; CHECK-LE: extsw 3, 3 1142} 1143 1144; Function Attrs: nounwind 1145define signext i32 @getsi3(<4 x i32> %vsi) { 1146entry: 1147 %vsi.addr = alloca <4 x i32>, align 16 1148 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1149 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1150 %vecext = extractelement <4 x i32> %0, i32 3 1151 ret i32 %vecext 1152; CHECK-LABEL: @getsi3 1153; CHECK: xxswapd [[SHL:[0-9]+]], 34 1154; CHECK: mfvsrwz 3, [[SHL]] 1155; CHECK: extsw 3, 3 1156; CHECK-LE-LABEL: @getsi3 1157; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1158; CHECK-LE: mfvsrwz 3, [[SHL]] 1159; CHECK-LE: extsw 3, 3 1160} 1161 1162; Function Attrs: nounwind 1163define zeroext i32 @getui0(<4 x i32> %vui) { 1164entry: 1165 %vui.addr = alloca <4 x i32>, align 16 1166 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1167 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1168 %vecext = extractelement <4 x i32> %0, i32 0 1169 ret i32 %vecext 1170; CHECK-LABEL: @getui0 1171; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1172; CHECK: mfvsrwz 3, [[SHL]] 1173; CHECK: clrldi 3, 3, 32 1174; CHECK-LE-LABEL: @getui0 1175; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1176; CHECK-LE: mfvsrwz 3, [[SHL]] 1177; CHECK-LE: clrldi 3, 3, 32 1178} 1179 1180; Function Attrs: nounwind 1181define zeroext i32 @getui1(<4 x i32> %vui) { 1182entry: 1183 %vui.addr = alloca <4 x i32>, align 16 1184 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1185 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1186 %vecext = extractelement <4 x i32> %0, i32 1 1187 ret i32 %vecext 1188; CHECK-LABEL: @getui1 1189; CHECK: mfvsrwz 3, 34 1190; CHECK: clrldi 3, 3, 32 1191; CHECK-LE-LABEL: @getui1 1192; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1193; CHECK-LE: mfvsrwz 3, [[SHL]] 1194; CHECK-LE: clrldi 3, 3, 32 1195} 1196 1197; Function Attrs: nounwind 1198define zeroext i32 @getui2(<4 x i32> %vui) { 1199entry: 1200 %vui.addr = alloca <4 x i32>, align 16 1201 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1202 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1203 %vecext = extractelement <4 x i32> %0, i32 2 1204 ret i32 %vecext 1205; CHECK-LABEL: @getui2 1206; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1207; CHECK: mfvsrwz 3, [[SHL]] 1208; CHECK: clrldi 3, 3, 32 1209; CHECK-LE-LABEL: @getui2 1210; CHECK-LE: mfvsrwz 3, 34 1211; CHECK-LE: clrldi 3, 3, 32 1212} 1213 1214; Function Attrs: nounwind 1215define zeroext i32 @getui3(<4 x i32> %vui) { 1216entry: 1217 %vui.addr = alloca <4 x i32>, align 16 1218 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1219 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1220 %vecext = extractelement <4 x i32> %0, i32 3 1221 ret i32 %vecext 1222; CHECK-LABEL: @getui3 1223; CHECK: xxswapd [[SHL:[0-9]+]], 34 1224; CHECK: mfvsrwz 3, [[SHL]] 1225; CHECK: clrldi 3, 3, 32 1226; CHECK-LE-LABEL: @getui3 1227; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1228; CHECK-LE: mfvsrwz 3, [[SHL]] 1229; CHECK-LE: clrldi 3, 3, 32 1230} 1231 1232; Function Attrs: nounwind 1233define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) { 1234entry: 1235 %vsi.addr = alloca <4 x i32>, align 16 1236 %i.addr = alloca i32, align 4 1237 store <4 x i32> %vsi, <4 x i32>* %vsi.addr, align 16 1238 store i32 %i, i32* %i.addr, align 4 1239 %0 = load <4 x i32>, <4 x i32>* %vsi.addr, align 16 1240 %1 = load i32, i32* %i.addr, align 4 1241 %vecext = extractelement <4 x i32> %0, i32 %1 1242 ret i32 %vecext 1243; CHECK-LABEL: @getvelsi 1244; CHECK-LE-LABEL: @getvelsi 1245; FIXME: add check patterns when variable element extraction is implemented 1246} 1247 1248; Function Attrs: nounwind 1249define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) { 1250entry: 1251 %vui.addr = alloca <4 x i32>, align 16 1252 %i.addr = alloca i32, align 4 1253 store <4 x i32> %vui, <4 x i32>* %vui.addr, align 16 1254 store i32 %i, i32* %i.addr, align 4 1255 %0 = load <4 x i32>, <4 x i32>* %vui.addr, align 16 1256 %1 = load i32, i32* %i.addr, align 4 1257 %vecext = extractelement <4 x i32> %0, i32 %1 1258 ret i32 %vecext 1259; CHECK-LABEL: @getvelui 1260; CHECK-LE-LABEL: @getvelui 1261; FIXME: add check patterns when variable element extraction is implemented 1262} 1263 1264; Function Attrs: nounwind 1265define i64 @getsl0(<2 x i64> %vsl) { 1266entry: 1267 %vsl.addr = alloca <2 x i64>, align 16 1268 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1269 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1270 %vecext = extractelement <2 x i64> %0, i32 0 1271 ret i64 %vecext 1272; CHECK-LABEL: @getsl0 1273; CHECK: mfvsrd 3, 34 1274; CHECK-LE-LABEL: @getsl0 1275; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 1276; CHECK-LE: mfvsrd 3, [[SWP]] 1277} 1278 1279; Function Attrs: nounwind 1280define i64 @getsl1(<2 x i64> %vsl) { 1281entry: 1282 %vsl.addr = alloca <2 x i64>, align 16 1283 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1284 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1285 %vecext = extractelement <2 x i64> %0, i32 1 1286 ret i64 %vecext 1287; CHECK-LABEL: @getsl1 1288; CHECK: xxswapd [[SWP:[0-9]+]], 34 1289; CHECK: mfvsrd 3, [[SWP]] 1290; CHECK-LE-LABEL: @getsl1 1291; CHECK-LE: mfvsrd 3, 34 1292} 1293 1294; Function Attrs: nounwind 1295define i64 @getul0(<2 x i64> %vul) { 1296entry: 1297 %vul.addr = alloca <2 x i64>, align 16 1298 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1299 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1300 %vecext = extractelement <2 x i64> %0, i32 0 1301 ret i64 %vecext 1302; CHECK-LABEL: @getul0 1303; CHECK: mfvsrd 3, 34 1304; CHECK-LE-LABEL: @getul0 1305; CHECK-LE: xxswapd [[SWP:[0-9]+]], 34 1306; CHECK-LE: mfvsrd 3, [[SWP]] 1307} 1308 1309; Function Attrs: nounwind 1310define i64 @getul1(<2 x i64> %vul) { 1311entry: 1312 %vul.addr = alloca <2 x i64>, align 16 1313 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1314 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1315 %vecext = extractelement <2 x i64> %0, i32 1 1316 ret i64 %vecext 1317; CHECK-LABEL: @getul1 1318; CHECK: xxswapd [[SWP:[0-9]+]], 34 1319; CHECK: mfvsrd 3, [[SWP]] 1320; CHECK-LE-LABEL: @getul1 1321; CHECK-LE: mfvsrd 3, 34 1322} 1323 1324; Function Attrs: nounwind 1325define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) { 1326entry: 1327 %vsl.addr = alloca <2 x i64>, align 16 1328 %i.addr = alloca i32, align 4 1329 store <2 x i64> %vsl, <2 x i64>* %vsl.addr, align 16 1330 store i32 %i, i32* %i.addr, align 4 1331 %0 = load <2 x i64>, <2 x i64>* %vsl.addr, align 16 1332 %1 = load i32, i32* %i.addr, align 4 1333 %vecext = extractelement <2 x i64> %0, i32 %1 1334 ret i64 %vecext 1335; CHECK-LABEL: @getvelsl 1336; CHECK-LE-LABEL: @getvelsl 1337; FIXME: add check patterns when variable element extraction is implemented 1338} 1339 1340; Function Attrs: nounwind 1341define i64 @getvelul(<2 x i64> %vul, i32 signext %i) { 1342entry: 1343 %vul.addr = alloca <2 x i64>, align 16 1344 %i.addr = alloca i32, align 4 1345 store <2 x i64> %vul, <2 x i64>* %vul.addr, align 16 1346 store i32 %i, i32* %i.addr, align 4 1347 %0 = load <2 x i64>, <2 x i64>* %vul.addr, align 16 1348 %1 = load i32, i32* %i.addr, align 4 1349 %vecext = extractelement <2 x i64> %0, i32 %1 1350 ret i64 %vecext 1351; CHECK-LABEL: @getvelul 1352; CHECK-LE-LABEL: @getvelul 1353; FIXME: add check patterns when variable element extraction is implemented 1354} 1355 1356; Function Attrs: nounwind 1357define float @getf0(<4 x float> %vf) { 1358entry: 1359 %vf.addr = alloca <4 x float>, align 16 1360 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1361 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1362 %vecext = extractelement <4 x float> %0, i32 0 1363 ret float %vecext 1364; CHECK-LABEL: @getf0 1365; CHECK: xscvspdpn 1, 34 1366; CHECK-LE-LABEL: @getf0 1367; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1368; CHECK-LE: xscvspdpn 1, [[SHL]] 1369} 1370 1371; Function Attrs: nounwind 1372define float @getf1(<4 x float> %vf) { 1373entry: 1374 %vf.addr = alloca <4 x float>, align 16 1375 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1376 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1377 %vecext = extractelement <4 x float> %0, i32 1 1378 ret float %vecext 1379; CHECK-LABEL: @getf1 1380; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1381; CHECK: xscvspdpn 1, [[SHL]] 1382; CHECK-LE-LABEL: @getf1 1383; CHECK-LE: xxswapd [[SHL:[0-9]+]], 34 1384; CHECK-LE: xscvspdpn 1, [[SHL]] 1385} 1386 1387; Function Attrs: nounwind 1388define float @getf2(<4 x float> %vf) { 1389entry: 1390 %vf.addr = alloca <4 x float>, align 16 1391 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1392 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1393 %vecext = extractelement <4 x float> %0, i32 2 1394 ret float %vecext 1395; CHECK-LABEL: @getf2 1396; CHECK: xxswapd [[SHL:[0-9]+]], 34 1397; CHECK: xscvspdpn 1, [[SHL]] 1398; CHECK-LE-LABEL: @getf2 1399; CHECK-LE: xxsldwi [[SHL:[0-9]+]], 34, 34, 1 1400; CHECK-LE: xscvspdpn 1, [[SHL]] 1401} 1402 1403; Function Attrs: nounwind 1404define float @getf3(<4 x float> %vf) { 1405entry: 1406 %vf.addr = alloca <4 x float>, align 16 1407 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1408 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1409 %vecext = extractelement <4 x float> %0, i32 3 1410 ret float %vecext 1411; CHECK-LABEL: @getf3 1412; CHECK: xxsldwi [[SHL:[0-9]+]], 34, 34, 3 1413; CHECK: xscvspdpn 1, [[SHL]] 1414; CHECK-LE-LABEL: @getf3 1415; CHECK-LE: xscvspdpn 1, 34 1416} 1417 1418; Function Attrs: nounwind 1419define float @getvelf(<4 x float> %vf, i32 signext %i) { 1420entry: 1421 %vf.addr = alloca <4 x float>, align 16 1422 %i.addr = alloca i32, align 4 1423 store <4 x float> %vf, <4 x float>* %vf.addr, align 16 1424 store i32 %i, i32* %i.addr, align 4 1425 %0 = load <4 x float>, <4 x float>* %vf.addr, align 16 1426 %1 = load i32, i32* %i.addr, align 4 1427 %vecext = extractelement <4 x float> %0, i32 %1 1428 ret float %vecext 1429; CHECK-LABEL: @getvelf 1430; CHECK-LE-LABEL: @getvelf 1431; FIXME: add check patterns when variable element extraction is implemented 1432} 1433 1434; Function Attrs: nounwind 1435define double @getd0(<2 x double> %vd) { 1436entry: 1437 %vd.addr = alloca <2 x double>, align 16 1438 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1439 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1440 %vecext = extractelement <2 x double> %0, i32 0 1441 ret double %vecext 1442; CHECK-LABEL: @getd0 1443; CHECK: xxlor 1, 34, 34 1444; CHECK-LE-LABEL: @getd0 1445; CHECK-LE: xxswapd 1, 34 1446} 1447 1448; Function Attrs: nounwind 1449define double @getd1(<2 x double> %vd) { 1450entry: 1451 %vd.addr = alloca <2 x double>, align 16 1452 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1453 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1454 %vecext = extractelement <2 x double> %0, i32 1 1455 ret double %vecext 1456; CHECK-LABEL: @getd1 1457; CHECK: xxswapd 1, 34 1458; CHECK-LE-LABEL: @getd1 1459; CHECK-LE: xxlor 1, 34, 34 1460} 1461 1462; Function Attrs: nounwind 1463define double @getveld(<2 x double> %vd, i32 signext %i) { 1464entry: 1465 %vd.addr = alloca <2 x double>, align 16 1466 %i.addr = alloca i32, align 4 1467 store <2 x double> %vd, <2 x double>* %vd.addr, align 16 1468 store i32 %i, i32* %i.addr, align 4 1469 %0 = load <2 x double>, <2 x double>* %vd.addr, align 16 1470 %1 = load i32, i32* %i.addr, align 4 1471 %vecext = extractelement <2 x double> %0, i32 %1 1472 ret double %vecext 1473; CHECK-LABEL: @getveld 1474; CHECK-LE-LABEL: @getveld 1475; FIXME: add check patterns when variable element extraction is implemented 1476} 1477