| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-uminv.ll | 5 ; CHECK: uminv.8b b[[REG:[0-9]+]], v0
10 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a) nounwind
28 ; CHECK: uminv.4h h[[REG:[0-9]+]], v0
33 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a) nounwind
49 ; CHECK: uminv.8h h[[REG:[0-9]+]], v0
54 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16> %a) nounwind
70 ; CHECK: uminv.16b b[[REG:[0-9]+]], v0
75 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %a) nounwind
91 ; CHECK: uminv.8b b[[REGNUM:[0-9]+]], v1
95 %0 = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a2)
[all …]
|
| D | arm64-neon-across.ll | 21 declare i32 @llvm.aarch64.neon.uminv.i32.v4i32(<4 x i32>)
23 declare i32 @llvm.aarch64.neon.uminv.i32.v8i16(<8 x i16>)
25 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>)
33 declare i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16>)
35 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>)
273 ; CHECK: uminv b{{[0-9]+}}, {{v[0-9]+}}.8b
275 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %a)
276 %0 = trunc i32 %uminv.i to i8
282 ; CHECK: uminv h{{[0-9]+}}, {{v[0-9]+}}.4h
284 %uminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v4i16(<4 x i16> %a)
[all …]
|
| D | arm64-vecCmpBr.ll | 9 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
16 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
34 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
42 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
151 ; CHECK: uminv.8b b[[REGNO1:[0-9]+]], v0
158 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8> %0) #3
174 ; CHECK: uminv.16b b[[REGNO1:[0-9]+]], v0
181 %vminv.i = tail call i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8> %0) #3
199 declare i32 @llvm.aarch64.neon.uminv.i32.v16i8(<16 x i8>) #2
201 declare i32 @llvm.aarch64.neon.uminv.i32.v8i8(<8 x i8>) #2
|
| D | aarch64-minmaxv.ll | 220 ; CHECK: uminv {{b[0-9]+}}, {{v[0-9]+}}.16b
242 ; CHECK: uminv {{h[0-9]+}}, {{v[0-9]+}}.8h
261 ; CHECK: uminv {{s[0-9]+}}, {{v[0-9]+}}.4s
277 ; CHECK-NOT: uminv
372 ; CHECK: uminv {{h[0-9]+}}, [[V0]]
397 ; CHECK-NEXT: uminv {{s[0-9]+}}, [[V0]]
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-across.s | 69 uminv b0, v1.8b
70 uminv b0, v1.16b
71 uminv h0, v1.4h
72 uminv h0, v1.8h
73 uminv s0, v1.4s
|
| D | neon-diagnostics.s | 3776 uminv s0, v1.2s
3798 uminv d0, v1.2d define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2265 __ uminv(b0, v17.V16B()); in GenerateTestSequenceNEON() local
2266 __ uminv(b0, v31.V8B()); in GenerateTestSequenceNEON() local
2267 __ uminv(h24, v0.V4H()); in GenerateTestSequenceNEON() local
2268 __ uminv(h29, v14.V8H()); in GenerateTestSequenceNEON() local
2269 __ uminv(s30, v3.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4411 DEFINE_TEST_NEON_ACROSS(uminv, Basic)
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 1922 0x~~~~~~~~~~~~~~~~ 6e31aa20 uminv b0, v17.16b
1923 0x~~~~~~~~~~~~~~~~ 2e31abe0 uminv b0, v31.8b
1924 0x~~~~~~~~~~~~~~~~ 2e71a818 uminv h24, v0.4h
1925 0x~~~~~~~~~~~~~~~~ 6e71a9dd uminv h29, v14.8h
1926 0x~~~~~~~~~~~~~~~~ 6eb1a87e uminv s30, v3.4s
|
| D | log-disasm-colour | 1922 0x~~~~~~~~~~~~~~~~ 6e31aa20 uminv b0, v17.16b
1923 0x~~~~~~~~~~~~~~~~ 2e31abe0 uminv b0, v31.8b
1924 0x~~~~~~~~~~~~~~~~ 2e71a818 uminv h24, v0.4h
1925 0x~~~~~~~~~~~~~~~~ 6e71a9dd uminv h29, v14.8h
1926 0x~~~~~~~~~~~~~~~~ 6eb1a87e uminv s30, v3.4s
|
| D | log-all | 5147 0x~~~~~~~~~~~~~~~~ 6e31aa20 uminv b0, v17.16b
5149 0x~~~~~~~~~~~~~~~~ 2e31abe0 uminv b0, v31.8b
5151 0x~~~~~~~~~~~~~~~~ 2e71a818 uminv h24, v0.4h
5153 0x~~~~~~~~~~~~~~~~ 6e71a9dd uminv h29, v14.8h
5155 0x~~~~~~~~~~~~~~~~ 6eb1a87e uminv s30, v3.4s
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 2226 void uminv(const VRegister& vd, const VRegister& vn);
|
| D | simulator-aarch64.h | 2437 LogicVRegister uminv(VectorFormat vform,
|
| D | macro-assembler-aarch64.h | 2324 V(uminv, Uminv) \
|
| D | simulator-aarch64.cc | 3724 uminv(vf, rd, rn); in VisitNEONAcrossLanes()
|
| D | logic-aarch64.cc | 1630 LogicVRegister Simulator::uminv(VectorFormat vform, in uminv() function in vixl::aarch64::Simulator
|
| D | assembler-aarch64.cc | 3487 V(uminv, NEON_UMINV, true)
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4226 void uminv(const VRegister& vd,
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 4129 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
|
| /external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/ |
| D | Intrinsics.gen | 318 aarch64_neon_uminv, // llvm.aarch64.neon.uminv
6376 "llvm.aarch64.neon.uminv",
14316 1, // llvm.aarch64.neon.uminv
|
| /external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/ |
| D | Intrinsics.gen | 310 aarch64_neon_uminv, // llvm.aarch64.neon.uminv
6334 "llvm.aarch64.neon.uminv",
14219 1, // llvm.aarch64.neon.uminv
|
| /external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/ |
| D | Intrinsics.gen | 318 aarch64_neon_uminv, // llvm.aarch64.neon.uminv
6376 "llvm.aarch64.neon.uminv",
14316 1, // llvm.aarch64.neon.uminv
|
| /external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/ |
| D | Intrinsics.gen | 318 aarch64_neon_uminv, // llvm.aarch64.neon.uminv
6376 "llvm.aarch64.neon.uminv",
14316 1, // llvm.aarch64.neon.uminv
|