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Searched refs:v_add_i32 (Results 1 – 17 of 17) sorted by relevance

/external/llvm/test/CodeGen/AMDGPU/
Dadd_i64.ll7 ; SI: v_add_i32
22 ; SI: v_add_i32
35 ; SI: v_add_i32
57 ; SI: v_add_i32
59 ; SI: v_add_i32
Dsminmax.ll22 ; GCN: v_add_i32
63 ; GCN: v_add_i32
64 ; GCN: v_add_i32
126 ; GCN: v_add_i32
127 ; GCN: v_add_i32
128 ; GCN: v_add_i32
129 ; GCN: v_add_i32
Duaddo.ll40 ; SI: v_add_i32
71 ; SI: v_add_i32
Dmove-addr64-rsrc-dead-subreg-writes.ll6 ; FIXME: We should be able to use the SGPR directly as src0 to v_add_i32
Dllvm.AMDGPU.bfe.u32.ll77 ; SI: v_add_i32
92 ; SI: v_add_i32
107 ; SI: v_add_i32
121 ; SI: v_add_i32
136 ; SI: v_add_i32
151 ; SI: v_add_i32
Dsdiv.ll40 ; SI: v_add_i32
43 ; SI: v_add_i32
Dextractelt-to-trunc.ll34 ; GCN: v_add_i32
Dsaddo.ll52 ; SI: v_add_i32
Dsplit-scalar-i64-add.ll36 ; SI: v_add_i32
Dlocal-stack-slot-bug.ll4 ; This used to fail due to a v_add_i32 instruction with an illegal immediate
Dadd.ll139 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
Dcopy-illegal-type.ll76 ; SI-DAG: v_add_i32
Dcvt_f32_ubyte.ll97 ; SI-DAG: v_add_i32
/external/llvm/test/MC/AMDGPU/regression/
Dbug28413.s28 v_add_i32 v0, vcc, 0.5, v0 label
32 v_add_i32 v0, vcc, 3.125, v0 label
/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s10 v_add_i32 v256, v0, v1 label
13 v_add_i32 v257, v0, v1 label
Dvop2.s99 v_add_i32 v0, vcc, 0.5, v0 label
103 v_add_i32 v0, vcc, 3.125, v0 label
267 v_add_i32 v1, vcc, v2, v3 label
271 v_add_i32 v1, s[0:1], v2, v3 label
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1568 defm V_ADD_I32 : VOP2bInst <vop2<0x25, 0x19>, "v_add_i32",
3558 def : MnemonicAlias<"v_add_u32", "v_add_i32">;