| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vadd.ll | 95 ;CHECK: vaddhn.i16
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
104 ;CHECK: vaddhn.i32
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
113 ;CHECK: vaddhn.i64
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vaddhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vaddhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neont2-add-encoding.s | 127 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04]
128 vaddhn.i16 d16, q8, q9
129 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xef,0xa2,0x04]
130 vaddhn.i32 d16, q8, q9
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
|
| D | neon-add-encoding.s | 126 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2]
127 vaddhn.i16 d16, q8, q9
128 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2]
129 vaddhn.i32 d16, q8, q9
130 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
131 vaddhn.i64 d16, q8, q9
|
| /external/llvm/test/MC/ARM/ |
| D | neont2-add-encoding.s | 127 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xc0,0xef,0xa2,0x04]
128 vaddhn.i16 d16, q8, q9
129 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xd0,0xef,0xa2,0x04]
130 vaddhn.i32 d16, q8, q9
131 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xe0,0xef,0xa2,0x04]
132 vaddhn.i64 d16, q8, q9
|
| D | neon-add-encoding.s | 223 @ CHECK: vaddhn.i16 d16, q8, q9 @ encoding: [0xa2,0x04,0xc0,0xf2]
224 vaddhn.i16 d16, q8, q9
225 @ CHECK: vaddhn.i32 d16, q8, q9 @ encoding: [0xa2,0x04,0xd0,0xf2]
226 vaddhn.i32 d16, q8, q9
227 @ CHECK: vaddhn.i64 d16, q8, q9 @ encoding: [0xa2,0x04,0xe0,0xf2]
228 vaddhn.i64 d16, q8, q9
|
| /external/arm-neon-tests/ |
| D | Android.mk | 35 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
|
| D | ref_vaddhn.c | 45 #define INSN_NAME vaddhn
|
| D | Makefile.gcc | 56 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
|
| D | Makefile | 50 vqdmlsl_n vsri_n vsli_n vtst vaddhn vraddhn vaddl vaddw \
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vadd.ll | 126 ; CHECK: vaddhn.i16
135 ; CHECK: vaddhn.i32
144 ; CHECK: vaddhn.i64
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-neon-3vdiff.ll | 549 %vaddhn.i = add <8 x i16> %a, %b
550 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
559 %vaddhn.i = add <4 x i32> %a, %b
560 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
569 %vaddhn.i = add <2 x i64> %a, %b
570 %vaddhn1.i = lshr <2 x i64> %vaddhn.i, <i64 32, i64 32>
579 %vaddhn.i = add <8 x i16> %a, %b
580 %vaddhn1.i = lshr <8 x i16> %vaddhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
589 %vaddhn.i = add <4 x i32> %a, %b
590 %vaddhn1.i = lshr <4 x i32> %vaddhn.i, <i32 16, i32 16, i32 16, i32 16>
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 236 # CHECK: vaddhn.i16 d16, q8, q9
238 # CHECK: vaddhn.i32 d16, q8, q9
240 # CHECK: vaddhn.i64 d16, q8, q9
|
| D | neon.txt | 239 # CHECK: vaddhn.i16 d16, q8, q9
241 # CHECK: vaddhn.i32 d16, q8, q9
243 # CHECK: vaddhn.i64 d16, q8, q9
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 236 # CHECK: vaddhn.i16 d16, q8, q9
238 # CHECK: vaddhn.i32 d16, q8, q9
240 # CHECK: vaddhn.i64 d16, q8, q9
|
| D | neon.txt | 239 # CHECK: vaddhn.i16 d16, q8, q9
241 # CHECK: vaddhn.i32 d16, q8, q9
243 # CHECK: vaddhn.i64 d16, q8, q9
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 428 def OP_ADDHNHi : Op<(call "vcombine", $p0, (call "vaddhn", $p1, $p2))>;
514 def VADDHN : IInst<"vaddhn", "hkk", "silUsUiUl">;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3824 void vaddhn(
3826 void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vaddhn() function
3827 vaddhn(al, dt, rd, rn, rm); in vaddhn()
|
| D | disasm-aarch32.h | 1382 void vaddhn(
|
| D | assembler-aarch32.cc | 13386 void Assembler::vaddhn( in vaddhn() function in vixl::aarch32::Assembler
13411 Delegate(kVaddhn, &Assembler::vaddhn, cond, dt, rd, rn, rm); in vaddhn()
|
| D | disasm-aarch32.cc | 3918 void Disassembler::vaddhn( in vaddhn() function in vixl::aarch32::Disassembler
29058 vaddhn(CurrentCond(), in DecodeT32()
43211 vaddhn(al, in DecodeA32()
|
| D | macro-assembler-aarch32.h | 5659 vaddhn(cond, dt, rd, rn, rm); in Vaddhn()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3402 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4158 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
|