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/external/llvm/test/MC/ARM/
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dsimple-fp-encoding.s59 vcvt.f32.f64 s0, d16
60 vcvt.f64.f32 d16, s0
62 @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
63 @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
77 vcvt.f64.s32 d16, s0
78 vcvt.f32.s32 s0, s0
79 vcvt.f64.u32 d16, s0
80 vcvt.f32.u32 s0, s0
81 vcvt.s32.f64 s0, d16
82 vcvt.s32.f32 s0, s0
[all …]
Dfullfp16.s68 vcvt.f16.s32 s0, s0
69 vcvt.f16.u32 s0, s0
70 vcvt.s32.f16 s0, s0
71 vcvt.u32.f16 s0, s0
72 @ ARM: vcvt.f16.s32 s0, s0 @ encoding: [0xc0,0x09,0xb8,0xee]
73 @ ARM: vcvt.f16.u32 s0, s0 @ encoding: [0x40,0x09,0xb8,0xee]
74 @ ARM: vcvt.s32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbd,0xee]
75 @ ARM: vcvt.u32.f16 s0, s0 @ encoding: [0xc0,0x09,0xbc,0xee]
76 @ THUMB: vcvt.f16.s32 s0, s0 @ encoding: [0xb8,0xee,0xc0,0x09]
77 @ THUMB: vcvt.f16.u32 s0, s0 @ encoding: [0xb8,0xee,0x40,0x09]
[all …]
Dsingle-precision-fp.s78 vcvt.f64.s32 d9, s8
79 vcvt.f64.u32 d7, s6
80 vcvt.s32.f64 s5, d4
81 vcvt.u32.f64 s3, d2
84 vcvt.s16.f64 d3, d4, #1
85 vcvt.u16.f64 d5, d6, #2
86 vcvt.s32.f64 d7, d8, #3
87 vcvt.u32.f64 d9, d10, #4
88 vcvt.f64.s16 d11, d12, #3
89 vcvt.f64.u16 d13, d14, #2
[all …]
Dfullfp16-neon.s261 vcvt.s16.f16 d0, d1
262 vcvt.u16.f16 d0, d1
263 vcvt.f16.s16 d0, d1
264 vcvt.f16.u16 d0, d1
265 vcvt.s16.f16 q0, q1
266 vcvt.u16.f16 q0, q1
267 vcvt.f16.s16 q0, q1
268 vcvt.f16.u16 q0, q1
269 @ ARM: vcvt.s16.f16 d0, d1 @ encoding: [0x01,0x07,0xb7,0xf3]
270 @ ARM: vcvt.u16.f16 d0, d1 @ encoding: [0x81,0x07,0xb7,0xf3]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-convert-encoding.s3 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0x20,0x07,0xfb,0xf3]
4 vcvt.s32.f32 d16, d16
5 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xa0,0x07,0xfb,0xf3]
6 vcvt.u32.f32 d16, d16
7 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0x20,0x06,0xfb,0xf3]
8 vcvt.f32.s32 d16, d16
9 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xa0,0x06,0xfb,0xf3]
10 vcvt.f32.u32 d16, d16
11 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0x60,0x07,0xfb,0xf3]
12 vcvt.s32.f32 q8, q8
[all …]
Dneont2-convert-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dneont2-cmp-encoding.s5 @ CHECK: vcvt.s32.f32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x07]
6 vcvt.s32.f32 d16, d16
7 @ CHECK: vcvt.u32.f32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x07]
8 vcvt.u32.f32 d16, d16
9 @ CHECK: vcvt.f32.s32 d16, d16 @ encoding: [0xfb,0xff,0x20,0x06]
10 vcvt.f32.s32 d16, d16
11 @ CHECK: vcvt.f32.u32 d16, d16 @ encoding: [0xfb,0xff,0xa0,0x06]
12 vcvt.f32.u32 d16, d16
13 @ CHECK: vcvt.s32.f32 q8, q8 @ encoding: [0xfb,0xff,0x60,0x07]
14 vcvt.s32.f32 q8, q8
[all …]
Dsimple-fp-encoding.s51 @ CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
52 vcvt.f32.f64 s0, d16
54 @ CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
55 vcvt.f64.f32 d16, s0
69 @ CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
70 vcvt.f64.s32 d16, s0
72 @ CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
73 vcvt.f32.s32 s0, s0
75 @ CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
76 vcvt.f64.u32 d16, s0
[all …]
/external/llvm/test/CodeGen/ARM/
Dvcvt_combine.ll5 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2
9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
15 ; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3
19 %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
20 ret <2 x i32> %vcvt.i
26 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
31 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
32 ret <2 x i32> %vcvt.i
38 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
[all …]
Dfast-isel-conversion.ll11 ; ARM: vcvt.f32.s32 s0, s0
14 ; THUMB: vcvt.f32.s32 s0, s0
26 ; ARM: vcvt.f32.s32 s0, s0
30 ; THUMB: vcvt.f32.s32 s0, s0
42 ; ARM: vcvt.f32.s32 s0, s0
46 ; THUMB: vcvt.f32.s32 s0, s0
57 ; ARM: vcvt.f64.s32 d16, s0
60 ; THUMB: vcvt.f64.s32 d16, s0
72 ; ARM: vcvt.f64.s32 d16, s0
76 ; THUMB: vcvt.f64.s32 d16, s0
[all …]
D2011-11-09-IllegalVectorFPIntConvert.ll5 ; CHECK: vcvt.s32.f64
6 ; CHECK: vcvt.s32.f64
14 ; CHECK: vcvt.u32.f64
15 ; CHECK: vcvt.u32.f64
23 ; CHECK: vcvt.f64.s32
24 ; CHECK: vcvt.f64.s32
32 ; CHECK: vcvt.f64.u32
33 ; CHECK: vcvt.f64.u32
Dvdiv_combine.ll17 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
18 %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
33 %vcvt.i = uitofp <2 x i32> %vecinit2.i to <2 x float>
34 %div.i = fdiv <2 x float> %vcvt.i, <float 8.000000e+00, float 8.000000e+00>
47 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
48 %div.i = fdiv <2 x float> %vcvt.i, <float 0x401B333340000000, float 0x401B333340000000>
61 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
62 %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
75 %vcvt.i = sitofp <2 x i32> %vecinit2.i to <2 x float>
76 %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
[all …]
Dneon_fpconv.ll5 ; CHECK: vcvt.f32.f64 [[S0:s[0-9]+]], [[D0:d[0-9]+]]
6 ; CHECK: vcvt.f32.f64 [[S1:s[0-9]+]], [[D1:d[0-9]+]]
12 ; CHECK: vcvt.f64.f32 [[D0:d[0-9]+]], [[S0:s[0-9]+]]
13 ; CHECK: vcvt.f64.f32 [[D1:d[0-9]+]], [[S1:s[0-9]+]]
24 ; CHECK-NEXT: vcvt.f64.s32
25 ; CHECK-NEXT: vcvt.f64.s32
36 ; CHECK-NEXT: vcvt.f64.u32
37 ; CHECK-NEXT: vcvt.f64.u32
Dfpconv.ll6 ;CHECK-VFP: vcvt.f32.f64
16 ;CHECK-VFP: vcvt.f64.f32
26 ;CHECK-VFP: vcvt.s32.f32
36 ;CHECK-VFP: vcvt.u32.f32
46 ;CHECK-VFP: vcvt.s32.f64
56 ;CHECK-VFP: vcvt.u32.f64
66 ;CHECK-VFP: vcvt.f32.s32
76 ;CHECK-VFP: vcvt.f64.s32
86 ;CHECK-VFP: vcvt.f32.u32
96 ;CHECK-VFP: vcvt.f64.u32
Dvcvt.ll5 ;CHECK: vcvt.s32.f32
13 ;CHECK: vcvt.u32.f32
21 ;CHECK: vcvt.f32.s32
29 ;CHECK: vcvt.f32.u32
37 ;CHECK: vcvt.s32.f32
45 ;CHECK: vcvt.u32.f32
53 ;CHECK: vcvt.f32.s32
61 ;CHECK: vcvt.f32.u32
69 ;CHECK: vcvt.s32.f32
77 ;CHECK: vcvt.u32.f32
[all …]
Dfp_convert.ll21 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
24 ; NEON: vcvt.s32.f32 d0, [[D0]]
33 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
36 ; NEON: vcvt.u32.f32 d0, [[D0]]
45 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
47 ; NEON: vcvt.f32.u32 d
56 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
58 ; NEON: vcvt.f32.s32 d
/external/llvm/test/CodeGen/AArch64/
Dfcvt_combine.ll9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
10 ret <2 x i32> %vcvt.i
19 %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
20 ret <4 x i32> %vcvt.i
29 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i64>
30 ret <2 x i64> %vcvt.i
41 %vcvt.i = fptosi <2 x double> %mul.i to <2 x i32>
42 ret <2 x i32> %vcvt.i
52 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i16>
53 ret <2 x i16> %vcvt.i
[all …]
Darm64-vcvt_su32_f32.ll7 %vcvt.i = fptosi <2 x float> %a to <2 x i32>
8 ret <2 x i32> %vcvt.i
15 %vcvt.i = fptoui <2 x float> %a to <2 x i32>
16 ret <2 x i32> %vcvt.i
23 %vcvt.i = fptosi <4 x float> %a to <4 x i32>
24 ret <4 x i32> %vcvt.i
31 %vcvt.i = fptoui <4 x float> %a to <4 x i32>
32 ret <4 x i32> %vcvt.i
Dfdiv_combine.ll9 %vcvt.i = sitofp <2 x i32> %in to <2 x float>
10 %div.i = fdiv <2 x float> %vcvt.i, <float 16.0, float 16.0>
20 %vcvt.i = uitofp <2 x i32> %in to <2 x float>
21 %div.i = fdiv <2 x float> %vcvt.i, <float 8.0, float 8.0>
33 %vcvt.i = sitofp <2 x i32> %in to <2 x float>
34 %div.i = fdiv <2 x float> %vcvt.i, <float 9.0, float 9.0>
46 %vcvt.i = sitofp <2 x i32> %in to <2 x float>
47 %div.i = fdiv <2 x float> %vcvt.i, <float 0x4200000000000000, float 0x4200000000000000>
57 %vcvt.i = sitofp <2 x i32> %in to <2 x float>
58 %div.i = fdiv <2 x float> %vcvt.i, <float 0x41F0000000000000, float 0x41F0000000000000>
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dfp_convert.ll8 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
11 ; NEON: vcvt.s32.f32 d0, [[D0]]
20 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
23 ; NEON: vcvt.u32.f32 d0, [[D0]]
32 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
34 ; NEON: vcvt.f32.u32 d0, d0
43 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
45 ; NEON: vcvt.f32.s32 d0, d0
Dvcvt.ll5 ;CHECK: vcvt.s32.f32
13 ;CHECK: vcvt.u32.f32
21 ;CHECK: vcvt.f32.s32
29 ;CHECK: vcvt.f32.u32
37 ;CHECK: vcvt.s32.f32
45 ;CHECK: vcvt.u32.f32
53 ;CHECK: vcvt.f32.s32
61 ;CHECK: vcvt.f32.u32
69 ;CHECK: vcvt.s32.f32
77 ;CHECK: vcvt.u32.f32
[all …]
Dfpconv.ll6 ;CHECK-VFP: vcvt.f32.f64
16 ;CHECK-VFP: vcvt.f64.f32
26 ;CHECK-VFP: vcvt.s32.f32
36 ;CHECK-VFP: vcvt.u32.f32
46 ;CHECK-VFP: vcvt.s32.f64
56 ;CHECK-VFP: vcvt.u32.f64
66 ;CHECK-VFP: vcvt.f32.s32
76 ;CHECK-VFP: vcvt.f64.s32
86 ;CHECK-VFP: vcvt.f32.u32
96 ;CHECK-VFP: vcvt.f64.u32

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