1; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s 2 3; Test signed conversion. 4; CHECK-LABEL: @t0 5; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2 6; CHECK: bx lr 7define <2 x i32> @t0(<2 x float> %in) { 8 %mul.i = fmul <2 x float> %in, <float 4.0, float 4.0> 9 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> 10 ret <2 x i32> %vcvt.i 11} 12 13; Test unsigned conversion. 14; CHECK-LABEL: @t1 15; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3 16; CHECK: bx lr 17define <2 x i32> @t1(<2 x float> %in) { 18 %mul.i = fmul <2 x float> %in, <float 8.0, float 8.0> 19 %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32> 20 ret <2 x i32> %vcvt.i 21} 22 23; Test which should not fold due to non-power of 2. 24; CHECK-LABEL: @t2 25; CHECK: vmul 26; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} 27; CHECK: bx lr 28define <2 x i32> @t2(<2 x float> %in) { 29entry: 30 %mul.i = fmul <2 x float> %in, <float 0x401B333340000000, float 0x401B333340000000> 31 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> 32 ret <2 x i32> %vcvt.i 33} 34 35; Test which should not fold due to power of 2 out of range. 36; CHECK-LABEL: @t3 37; CHECK: vmul 38; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}} 39; CHECK: bx lr 40define <2 x i32> @t3(<2 x float> %in) { 41 %mul.i = fmul <2 x float> %in, <float 0x4200000000000000, float 0x4200000000000000> 42 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> 43 ret <2 x i32> %vcvt.i 44} 45 46; Test which case where const is max power of 2 (i.e., 2^32). 47; CHECK-LABEL: @t4 48; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #32 49; CHECK: bx lr 50define <2 x i32> @t4(<2 x float> %in) { 51 %mul.i = fmul <2 x float> %in, <float 0x41F0000000000000, float 0x41F0000000000000> 52 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32> 53 ret <2 x i32> %vcvt.i 54} 55 56; Test quadword. 57; CHECK-LABEL: @t5 58; CHECK: vcvt.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}, #3 59; CHECK: bx lr 60define <4 x i32> @t5(<4 x float> %in) { 61 %mul.i = fmul <4 x float> %in, <float 8.0, float 8.0, float 8.0, float 8.0> 62 %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32> 63 ret <4 x i32> %vcvt.i 64} 65 66; CHECK-LABEL: test_illegal_fp_to_int: 67; CHECK: vcvt.s32.f32 {{q[0-9]+}}, {{q[0-9]+}}, #2 68define <3 x i32> @test_illegal_fp_to_int(<3 x float> %in) { 69 %scale = fmul <3 x float> %in, <float 4.0, float 4.0, float 4.0> 70 %val = fptosi <3 x float> %scale to <3 x i32> 71 ret <3 x i32> %val 72}