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Searched refs:vqdmulh (Results 1 – 25 of 28) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-mul-encoding.s50 vqdmulh.s16 d16, d16, d17
51 vqdmulh.s32 d16, d16, d17
52 vqdmulh.s16 q8, q8, q9
53 vqdmulh.s32 q8, q8, q9
54 vqdmulh.s16 d16, d17
55 vqdmulh.s32 d16, d17
56 vqdmulh.s16 q8, q9
57 vqdmulh.s32 q8, q9
58 vqdmulh.s16 d11, d2, d3[0]
60 @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf2]
[all …]
Dneont2-mul-encoding.s30 vqdmulh.s16 d16, d16, d17
31 vqdmulh.s32 d16, d16, d17
32 vqdmulh.s16 q8, q8, q9
33 vqdmulh.s32 q8, q8, q9
34 vqdmulh.s16 d11, d2, d3[0]
36 @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b]
37 @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b]
38 @ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b]
39 @ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b]
40 @ CHECK: vqdmulh.s16 d11, d2, d3[0] @ encoding: [0x92,0xef,0x43,0xbc]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-mul-encoding.s25 @ CHECK: vqdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xef,0xa1,0x0b]
26 vqdmulh.s16 d16, d16, d17
27 @ CHECK: vqdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xef,0xa1,0x0b]
28 vqdmulh.s32 d16, d16, d17
29 @ CHECK: vqdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xef,0xe2,0x0b]
30 vqdmulh.s16 q8, q8, q9
31 @ CHECK: vqdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xef,0xe2,0x0b]
32 vqdmulh.s32 q8, q8, q9
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvqdmul.ll7 ;CHECK: vqdmulh.s16
10 %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
16 ;CHECK: vqdmulh.s32
19 %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
25 ;CHECK: vqdmulh.s16
28 %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
34 ;CHECK: vqdmulh.s32
37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
44 ; CHECK: vqdmulh.s16 q0, q0, d2[1]
46 …%1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <…
[all …]
/external/llvm/test/CodeGen/ARM/
Dvqdmul.ll7 ;CHECK: vqdmulh.s16
10 %tmp3 = call <4 x i16> @llvm.arm.neon.vqdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
16 ;CHECK: vqdmulh.s32
19 %tmp3 = call <2 x i32> @llvm.arm.neon.vqdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
25 ;CHECK: vqdmulh.s16
28 %tmp3 = call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
34 ;CHECK: vqdmulh.s32
37 %tmp3 = call <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
44 ; CHECK: vqdmulh.s16 q0, q0, d2[1]
46 …%1 = tail call <8 x i16> @llvm.arm.neon.vqdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; <…
[all …]
/external/arm-neon-tests/
DAndroid.mk30 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
Dref_vqdmulh_n.c34 #define INSN vqdmulh
Dref_vqdmulh_lane.c34 #define INSN vqdmulh
Dref_vqdmulh.c34 #define INSN vqdmulh
DMakefile.gcc51 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
DMakefile45 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
/external/libjpeg-turbo/simd/
Djsimd_arm_neon.S760 vqdmulh.s16 q4, q2, XFIX_1_414213562
761 vqdmulh.s16 q6, q1, XFIX_2_613125930
765 vqdmulh.s16 q4, q1, XFIX_1_847759065
768 vqdmulh.s16 q6, q2, XFIX_1_414213562
770 vqdmulh.s16 q4, q5, XFIX_1_082392200
814 vqdmulh.s16 q4, q2, XFIX_1_414213562
815 vqdmulh.s16 q6, q1, XFIX_2_613125930
819 vqdmulh.s16 q4, q1, XFIX_1_847759065
822 vqdmulh.s16 q6, q2, XFIX_1_414213562
824 vqdmulh.s16 q4, q5, XFIX_1_082392200
[all …]
/external/vixl/src/aarch32/
Dassembler-aarch32.h5184 void vqdmulh(
5186 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqdmulh() function
5187 vqdmulh(al, dt, rd, rn, rm); in vqdmulh()
5190 void vqdmulh(
5192 void vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqdmulh() function
5193 vqdmulh(al, dt, rd, rn, rm); in vqdmulh()
5196 void vqdmulh(Condition cond,
5201 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vqdmulh() function
5202 vqdmulh(al, dt, rd, rn, rm); in vqdmulh()
5205 void vqdmulh(Condition cond,
[all …]
Ddisasm-aarch32.h2056 void vqdmulh(
2059 void vqdmulh(
2062 void vqdmulh(Condition cond,
2068 void vqdmulh(Condition cond,
Dassembler-aarch32.cc21517 void Assembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Assembler
21542 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
21545 void Assembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Assembler
21570 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
21573 void Assembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Assembler
21606 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
21609 void Assembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Assembler
21642 Delegate(kVqdmulh, &Assembler::vqdmulh, cond, dt, rd, rn, rm); in vqdmulh()
Ddisasm-aarch32.cc5799 void Disassembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Disassembler
5810 void Disassembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Disassembler
5821 void Disassembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Disassembler
5832 void Disassembler::vqdmulh( in vqdmulh() function in vixl::aarch32::Disassembler
25916 vqdmulh(CurrentCond(), in DecodeT32()
25972 vqdmulh(CurrentCond(), in DecodeT32()
29794 vqdmulh(CurrentCond(), in DecodeT32()
29858 vqdmulh(CurrentCond(), in DecodeT32()
39243 vqdmulh(al, in DecodeA32()
39297 vqdmulh(al, in DecodeA32()
[all …]
Dmacro-assembler-aarch32.h8683 vqdmulh(cond, dt, rd, rn, rm); in Vqdmulh()
8698 vqdmulh(cond, dt, rd, rn, rm); in Vqdmulh()
8716 vqdmulh(cond, dt, rd, rn, rm); in Vqdmulh()
8734 vqdmulh(cond, dt, rd, rn, rm); in Vqdmulh()
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt675 # CHECK: vqdmulh.s16 d16, d16, d17
677 # CHECK: vqdmulh.s32 d16, d16, d17
679 # CHECK: vqdmulh.s16 q8, q8, q9
681 # CHECK: vqdmulh.s32 q8, q8, q9
Dneon.txt779 # CHECK: vqdmulh.s16 d16, d16, d17
781 # CHECK: vqdmulh.s32 d16, d16, d17
783 # CHECK: vqdmulh.s16 q8, q8, q9
785 # CHECK: vqdmulh.s32 q8, q8, q9
/external/clang/include/clang/Basic/
Darm_neon.td375 def OP_QDMULH_LN : Op<(call "vqdmulh", $p0, (splat $p1, $p2))>;
478 def OP_SCALAR_QDMULH_LN : ScalarMulOp<"vqdmulh">;
525 def VQDMULH : SInst<"vqdmulh", "ddd", "siQsQi">;
1434 def SCALAR_SQDMULH : SInst<"vqdmulh", "sss", "SsSi">;
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt675 # CHECK: vqdmulh.s16 d16, d16, d17
677 # CHECK: vqdmulh.s32 d16, d16, d17
679 # CHECK: vqdmulh.s16 q8, q8, q9
681 # CHECK: vqdmulh.s32 q8, q8, q9
Dneon.txt779 # CHECK: vqdmulh.s16 d16, d16, d17
781 # CHECK: vqdmulh.s32 d16, d16, d17
783 # CHECK: vqdmulh.s16 q8, q8, q9
785 # CHECK: vqdmulh.s32 q8, q8, q9
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3448 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3451 "vqdmulh", "s", int_arm_neon_vqdmulh>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4232 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4235 "vqdmulh", "s", int_arm_neon_vqdmulh>;
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen625 arm_neon_vqdmulh, // llvm.arm.neon.vqdmulh
6683 "llvm.arm.neon.vqdmulh",
14623 1, // llvm.arm.neon.vqdmulh

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