| /external/libavc/encoder/arm/ |
| D | ih264e_half_pel.s | 355 …vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding…
357 …vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
373 …vshrn.s32 d28, q1, #8 @// shift by 8 and later we will shift by 2 more with rounding…
380 …vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
402 …vshrn.s32 d28, q11, #8 @// shift by 8 and later we will shift by 2 more with rounding…
460 …vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding…
462 …vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
478 …vshrn.s32 d28, q3, #8 @// shift by 8 and later we will shift by 2 more with rounding…
485 …vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
507 …vshrn.s32 d28, q11, #8 @// shift by 8 and later we will shift by 2 more with rounding…
[all …]
|
| /external/libhevc/common/arm/ |
| D | ihevc_inter_pred_luma_vert_w16inp_w16out.s | 207 vshrn.s32 d8, q4, #6
226 vshrn.s32 d10, q5, #6
251 vshrn.s32 d12, q6, #6
269 vshrn.s32 d14, q7, #6
296 vshrn.s32 d8, q4, #6
317 vshrn.s32 d10, q5, #6
338 vshrn.s32 d12, q6, #6
353 vshrn.s32 d14, q7, #6
367 vshrn.s32 d8, q4, #6
380 vshrn.s32 d10, q5, #6
[all …]
|
| D | ihevc_intra_pred_filters_chroma_mode_19_to_25.s | 263 vshrn.s16 d5,q1,#5 @idx = pos >> 5
392 vshrn.s16 d3,q1,#5 @idx = pos >> 5
492 vshrn.s16 d3,q1,#5 @idx = pos >> 5
|
| D | ihevc_intra_pred_chroma_mode_27_to_33.s | 153 vshrn.u16 d5,q1,#5 @idx = pos >> 5
284 vshrn.u16 d3,q1,#5 @idx = pos >> 5
380 vshrn.u16 d3,q1,#5 @idx = pos >> 5
|
| D | ihevc_intra_pred_luma_mode_27_to_33.s | 156 vshrn.u16 d5,q1,#5 @idx = pos >> 5
285 vshrn.u16 d3,q1,#5 @idx = pos >> 5
380 vshrn.u16 d3,q1,#5 @idx = pos >> 5
|
| D | ihevc_intra_pred_filters_luma_mode_19_to_25.s | 268 vshrn.s16 d5,q1,#5 @idx = pos >> 5
391 vshrn.s16 d3,q1,#5 @idx = pos >> 5
488 vshrn.s16 d3,q1,#5 @idx = pos >> 5
|
| /external/libjpeg-turbo/simd/ |
| D | jsimd_arm_neon.S | 429 vshrn.s32 ROW1L, q1, #16
437 vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
441 vshrn.s32 ROW2L, q1, #16
442 vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
451 vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
452 vshrn.s32 ROW3L, q5, #16
453 vshrn.s32 ROW0L, q6, #16
454 vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
478 vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
486 vshrn.s32 ROW6R, q1, #16
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neont2-shift-encoding.s | 87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
|
| D | neon-shift-encoding.s | 150 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
151 vshrn.i16 d16, q8, #8
152 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
153 vshrn.i32 d16, q8, #16
154 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
155 vshrn.i64 d16, q8, #32
|
| /external/llvm/test/MC/ARM/ |
| D | neont2-shift-encoding.s | 87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
|
| D | neon-shift-encoding.s | 273 vshrn.i16 d16, q8, #8
274 vshrn.i32 d16, q8, #16
275 vshrn.i64 d16, q8, #32
277 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
278 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
279 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vshrn.ll | 5 ;CHECK: vshrn.i16
13 ;CHECK: vshrn.i32
21 ;CHECK: vshrn.i64
|
| D | reg_sequence.ll | 18 ; CHECK: vshrn.i32
19 ; CHECK: vshrn.i32
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vshrn.ll | 5 ;CHECK: vshrn.i16
14 ;CHECK: vshrn.i32
23 ;CHECK: vshrn.i64
|
| D | reg_sequence.ll | 18 ; CHECK: vshrn.i32
19 ; CHECK: vshrn.i32
|
| /external/libavc/common/arm/ |
| D | ih264_resi_trans_quant_a9.s | 519 vshrn.s32 d0, q0, #1 @i4_value = (x0 + x1) >> 1;
520 vshrn.s32 d1, q1, #1 @i4_value = (x3 + x2) >> 1;
521 vshrn.s32 d2, q2, #1 @i4_value = (x0 - x1) >> 1;
522 vshrn.s32 d3, q3, #1 @i4_value = (x3 - x2) >> 1;
562 vshrn.u16 d14, q5, #8
563 vshrn.u16 d15, q6, #8
675 vshrn.u16 d14, q7, #8 @reduce nnz comparison to 1 bit
|
| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_arm_asm.S | 702 # asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14
703 # asm 2: vshrn.u64 <v23=d19,<d23=q1,#14
704 vshrn.u64 d19,q1,#14
714 # asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26
715 # asm 2: vshrn.u64 <v01=d21,<d01=q11,#26
716 vshrn.u64 d21,q11,#26
734 # asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20
735 # asm 2: vshrn.u64 <v23=d18,<mid=q0,#20
736 vshrn.u64 d18,q0,#20
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | loopfilter_8_neon.asm | 299 vshrn.u16 d30, q10, #4
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 1102 # CHECK: vshrn.i16 d16, q8, #8
1104 # CHECK: vshrn.i32 d16, q8, #16
1106 # CHECK: vshrn.i64 d16, q8, #32
|
| D | neon.txt | 1279 # CHECK: vshrn.i16 d16, q8, #8
1281 # CHECK: vshrn.i32 d16, q8, #16
1283 # CHECK: vshrn.i64 d16, q8, #32
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 1102 # CHECK: vshrn.i16 d16, q8, #8
1104 # CHECK: vshrn.i32 d16, q8, #16
1106 # CHECK: vshrn.i64 d16, q8, #32
|
| D | neon.txt | 1279 # CHECK: vshrn.i16 d16, q8, #8
1281 # CHECK: vshrn.i32 d16, q8, #16
1283 # CHECK: vshrn.i64 d16, q8, #32
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5672 void vshrn(Condition cond,
5677 void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { in vshrn() function
5678 vshrn(al, dt, rd, rm, operand); in vshrn()
|
| D | disasm-aarch32.h | 2341 void vshrn(Condition cond,
|
| D | disasm-aarch32.cc | 6619 void Disassembler::vshrn(Condition cond, in vshrn() function in vixl::aarch32::Disassembler
32123 vshrn(CurrentCond(), in DecodeT32()
32266 vshrn(CurrentCond(), in DecodeT32()
32409 vshrn(CurrentCond(), in DecodeT32()
32552 vshrn(CurrentCond(), in DecodeT32()
32694 vshrn(CurrentCond(), in DecodeT32()
44660 vshrn(al, in DecodeA32()
44795 vshrn(al, in DecodeA32()
44930 vshrn(al, in DecodeA32()
45065 vshrn(al, in DecodeA32()
[all …]
|