| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neon-sub-encoding.s | 97 @ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2]
98 vsubhn.i16 d16, q8, q9
99 @ CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2]
100 vsubhn.i32 d16, q8, q9
101 @ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2]
102 vsubhn.i64 d16, q8, q9
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vsub.ll | 95 ;CHECK: vsubhn.i16
98 %tmp3 = call <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
104 ;CHECK: vsubhn.i32
107 %tmp3 = call <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
113 ;CHECK: vsubhn.i64
116 %tmp3 = call <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
120 declare <8 x i8> @llvm.arm.neon.vsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
121 declare <4 x i16> @llvm.arm.neon.vsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
122 declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
|
| /external/llvm/test/MC/ARM/ |
| D | neon-sub-encoding.s | 123 @ CHECK: vsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf2]
124 vsubhn.i16 d16, q8, q9
125 @ CHECK: vsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf2]
126 vsubhn.i32 d16, q8, q9
127 @ CHECK: vsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf2]
128 vsubhn.i64 d16, q8, q9
|
| /external/arm-neon-tests/ |
| D | ref_vsubhn.c | 26 #define INSN_NAME vsubhn
|
| D | Android.mk | 36 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
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| D | Makefile.gcc | 57 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
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| D | Makefile | 51 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | machine-copy-prop.ll | 51 %vsubhn = sub <2 x i64> <i64 11, i64 0>, %t4
52 %vsubhn1 = lshr <2 x i64> %vsubhn, <i64 32, i64 32>
|
| D | arm64-neon-3vdiff.ll | 813 %vsubhn.i = sub <8 x i16> %a, %b
814 %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
823 %vsubhn.i = sub <4 x i32> %a, %b
824 %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>
833 %vsubhn.i = sub <2 x i64> %a, %b
834 %vsubhn1.i = lshr <2 x i64> %vsubhn.i, <i64 32, i64 32>
843 %vsubhn.i = sub <8 x i16> %a, %b
844 %vsubhn1.i = lshr <8 x i16> %vsubhn.i, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
853 %vsubhn.i = sub <4 x i32> %a, %b
854 %vsubhn1.i = lshr <4 x i32> %vsubhn.i, <i32 16, i32 16, i32 16, i32 16>
[all …]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vsub.ll | 95 ; CHECK: vsubhn.i16
104 ; CHECK: vsubhn.i32
113 ; CHECK: vsubhn.i64
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neon.txt | 1607 # CHECK: vsubhn.i16 d16, q8, q9
1609 # CHECK: vsubhn.i32 d16, q8, q9
1611 # CHECK: vsubhn.i64 d16, q8, q9
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neon.txt | 1607 # CHECK: vsubhn.i16 d16, q8, q9
1609 # CHECK: vsubhn.i32 d16, q8, q9
1611 # CHECK: vsubhn.i64 d16, q8, q9
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 430 def OP_SUBHNHi : Op<(call "vcombine", $p0, (call "vsubhn", $p1, $p2))>;
546 def VSUBHN : IInst<"vsubhn", "hkk", "silUsUiUl">;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5963 void vsubhn(
5965 void vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vsubhn() function
5966 vsubhn(al, dt, rd, rn, rm); in vsubhn()
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| D | disasm-aarch32.h | 2467 void vsubhn(
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| D | assembler-aarch32.cc | 26112 void Assembler::vsubhn( in vsubhn() function in vixl::aarch32::Assembler
26137 Delegate(kVsubhn, &Assembler::vsubhn, cond, dt, rd, rn, rm); in vsubhn()
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| D | disasm-aarch32.cc | 6891 void Disassembler::vsubhn( in vsubhn() function in vixl::aarch32::Disassembler
29160 vsubhn(CurrentCond(), in DecodeT32()
43304 vsubhn(al, in DecodeA32()
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| D | macro-assembler-aarch32.h | 10372 vsubhn(cond, dt, rd, rn, rm); in Vsubhn()
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3654 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 4697 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
|