| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-atomic.s | 6 casb w0, w1, [x2]
7 casab w0, w1, [x2]
8 caslb w0, w1, [x2]
9 casalb w0, w1, [x2]
16 casb w0, w1, [w2]
26 cash w0, w1, [x2]
27 casah w0, w1, [x2]
28 caslh w0, w1, [x2]
29 casalh w0, w1, [x2]
37 cas w0, w1, [x2]
[all …]
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| D | ldr-pseudo.s | 26 ldr w0, =0x10001
33 ldr w0, =0x10002
39 ldr w0, =0x10003
48 ldr w0, =0x10004
57 ldr w0, =0x10004
70 ldr w0, =0x10006
87 ldr w0, =0x10007
100 ldr w0, =foo
107 ldr w0, =f5
114 ldr w0, =f12
[all …]
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| D | arm64-mapping-across-sections.s | 4 add w0, w0, w0
8 add w0, w0, w0
16 add w0, w0, w0
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| D | mapping-across-sections.s | 4 add w0, w0, w0
8 add w0, w0, w0
16 add w0, w0, w0
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| D | armv8.1a-lor.s | 8 ldlarb w0,[x1]
9 ldlarh w0,[x1]
10 ldlar w0,[x1]
16 stllrb w0,[x1]
17 stllrh w0,[x1]
18 stllr w0,[x1]
36 ldlarb w0,[w1]
38 stllrb w0,[w1]
40 stllr w0,[w1]
|
| D | arm64-aliases.s | 113 neg w0, w1
114 ; CHECK: neg w0, w1
115 neg w0, w1, lsl #1
116 ; CHECK: neg w0, w1, lsl #1
121 negs w0, w1
122 ; CHECK: negs w0, w1
123 negs w0, w1, lsl #1
124 ; CHECK: negs w0, w1, lsl #1
140 mov w0, #0xffffffff
141 mov w0, #0xffffff00
[all …]
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| /external/llvm/test/CodeGen/AArch64/ |
| D | mul_pow2.ll | 8 ; CHECK: lsl w0, w0, #1
16 ; CHECK: add w0, w0, w0, lsl #1
24 ; CHECK: lsl w0, w0, #2
32 ; CHECK: add w0, w0, w0, lsl #2
41 ; CHECK: lsl {{w[0-9]+}}, w0, #3
42 ; CHECK: sub w0, {{w[0-9]+}}, w0
50 ; CHECK: lsl w0, w0, #3
58 ; CHECK: add w0, w0, w0, lsl #3
69 ; CHECK: neg w0, w0, lsl #1
77 ; CHECK: sub w0, w0, w0, lsl #2
[all …]
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| D | arm64-fast-isel-icmp.ll | 6 ; CHECK: cmp w0, #31
7 ; CHECK-NEXT: cset w0, eq
16 ; CHECK: cmn w0, #7
17 ; CHECK-NEXT: cset w0, eq
26 ; CHECK: cmp w0, w1
27 ; CHECK-NEXT: cset w0, eq
36 ; CHECK: cmp w0, w1
37 ; CHECK-NEXT: cset w0, ne
66 ; CHECK: cmp w0, w1
67 ; CHECK-NEXT: cset w0, hi
[all …]
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| D | arm64-fast-isel-conversion-fallback.ll | 9 ; CHECK: mov w0, [[REG]]
20 ; CHECK: mov w0, [[REG]]
29 ; CHECK: sbfx w0, w0, #0, #1
30 ; CHECK: scvtf s0, w0
40 ; CHECK: sxtb w0, w0
41 ; CHECK: scvtf s0, w0
51 ; CHECK: sxth w0, w0
52 ; CHECK: scvtf s0, w0
62 ; CHECK: scvtf s0, w0
82 ; CHECK: and w0, w0, #0x1
[all …]
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| D | fast-isel-logic-op.ll | 7 ; CHECK: and [[REG:w[0-9]+]], w0, w1
14 ; CHECK: and [[REG:w[0-9]+]], w0, w1
22 ; CHECK: and [[REG:w[0-9]+]], w0, w1
30 ; CHECK: and w0, w0, w1
44 ; CHECK: and {{w[0-9]+}}, w0, #0x1
51 ; CHECK: and {{w[0-9]+}}, w0, #0xf
58 ; CHECK: and {{w[0-9]+}}, w0, #0xff
65 ; CHECK: and w0, w0, #0xff
79 ; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #4
88 ; CHECK: and [[REG:w[0-9]+]], w0, w1, lsl #8
[all …]
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| D | arm64-shifted-sext.ll | 8 ; CHECK: add [[REG:w[0-9]+]], w0, #1
9 ; CHECK: sbfiz w0, [[REG]], #4, #8
20 ; CHECK: add [[REG:w[0-9]+]], w0, #1
21 ; CHECK: sbfx w0, [[REG]], #4, #4
32 ; CHECK: add [[REG:w[0-9]+]], w0, #1
33 ; CHECK: sbfiz w0, [[REG]], #8, #8
44 ; CHECK: add [[REG:w[0-9]+]], w0, #1
46 ; CHECK: asr w0, [[REG]], #8
57 ; CHECK: add [[REG:w[0-9]+]], w0, #1
58 ; CHECK: sbfiz w0, [[REG]], #4, #8
[all …]
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| D | arm64-arith.ll | 6 ; CHECK: add w0, w1, w0
15 ; CHECK: udiv w0, w0, w1
33 ; CHECK: sdiv w0, w0, w1
51 ; CHECK: lsl w0, w0, w1
69 ; CHECK: lsr w0, w0, w1
87 ; CHECK: asr w0, w0, w1
105 ; CHECK: add w0, w1, w0, sxth
115 ; CHECK: add w0, w1, w0, sxth #2
126 ; CHECK: and w8, w0, #0xffff
139 ; CHECK: add x0, x1, w0, uxtw
[all …]
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| D | arm64-crc32.ll | 5 ; CHECK: crc32b w0, w0, w1
13 ; CHECK: crc32h w0, w0, w1
21 ; CHECK: crc32w w0, w0, w1
28 ; CHECK: crc32x w0, w0, x1
35 ; CHECK: crc32cb w0, w0, w1
43 ; CHECK: crc32ch w0, w0, w1
51 ; CHECK: crc32cw w0, w0, w1
58 ; CHECK: crc32cx w0, w0, x1
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| D | arm64-fast-isel-conversion.ll | 8 ; CHECK: strb w0, [sp, #15]
14 ; CHECK: str w0, [sp, #8]
15 ; CHECK: ldr w0, [sp, #8]
16 ; CHECK: strh w0, [sp, #12]
17 ; CHECK: ldrh w0, [sp, #12]
18 ; CHECK: strb w0, [sp, #15]
19 ; CHECK: ldrb w0, [sp, #15]
48 ; CHECK: strb w0, [sp, #15]
52 ; CHECK: ldrb w0, [sp, #15]
53 ; CHECK: strh w0, [sp, #12]
[all …]
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| D | sdivpow2.ll | 6 ; CHECK: add w8, w0, #7
7 ; CHECK: cmp w0, #0
8 ; CHECK: csel w8, w8, w0, lt
9 ; CHECK: asr w0, w8, #3
16 ; CHECK: add w8, w0, #7
17 ; CHECK: cmp w0, #0
18 ; CHECK: csel w8, w8, w0, lt
19 ; CHECK: neg w0, w8, asr #3
26 ; CHECK: add w8, w0, #31
27 ; CHECK: cmp w0, #0
[all …]
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| D | fast-isel-folded-shift.ll | 7 ; CHECK: and [[REG:w[0-9]+]], w0, w8
16 ; CHECK: and [[REG:w[0-9]+]], w0, w8
25 ; CHECK: and w0, w0, w8
42 ; CHECK: orr [[REG:w[0-9]+]], w0, w8
51 ; CHECK: orr [[REG:w[0-9]+]], w0, w8
60 ; CHECK: orr w0, w0, w8
77 ; CHECK: eor [[REG:w[0-9]+]], w0, w8
86 ; CHECK: eor [[REG:w[0-9]+]], w0, w8
95 ; CHECK: eor w0, w0, w8
112 ; CHECK: add w0, w0, w8
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| /external/mesa3d/src/gallium/drivers/r600/sb/ |
| D | sb_bc_decoder.cpp | 54 CF_WORD0_EGCM w0(dw0); in decode_cf() local
55 bc.addr = w0.get_ADDR(); in decode_cf()
56 bc.jumptable_sel = w0.get_JUMPTABLE_SEL(); in decode_cf()
83 CF_WORD0_R6R7 w0(dw0); in decode_cf() local
84 bc.addr = w0.get_ADDR(); in decode_cf()
116 CF_ALU_WORD0_ALL w0(dw0); in decode_cf_alu() local
118 bc.kc[0].bank = w0.get_KCACHE_BANK0(); in decode_cf_alu()
119 bc.kc[1].bank = w0.get_KCACHE_BANK1(); in decode_cf_alu()
120 bc.kc[0].mode = w0.get_KCACHE_MODE0(); in decode_cf_alu()
122 bc.addr = w0.get_ADDR(); in decode_cf_alu()
[all …]
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| /external/tcpdump/ |
| D | print-tipc.c | 66 uint32_t w0; member
70 #define TIPC_VER(w0) (((w0) >> 29) & 0x07) argument
71 #define TIPC_USER(w0) (((w0) >> 25) & 0x0F) argument
72 #define TIPC_HSIZE(w0) (((w0) >> 21) & 0x0F) argument
73 #define TIPC_MSIZE(w0) (((w0) >> 0) & 0xFFFF) argument
110 uint32_t w0; member
124 uint32_t w0; member
146 uint32_t w0; member
161 uint32_t w0, w1, w2; in print_payload() local
176 w0 = EXTRACT_32BITS(&ap->w0); in print_payload()
[all …]
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-atomic.txt | 11 # CHECK: casb w0, w1, [x2]
12 # CHECK: casab w0, w1, [x2]
13 # CHECK: caslb w0, w1, [x2]
14 # CHECK: casalb w0, w1, [x2]
15 # CHECK: cash w0, w1, [x2]
16 # CHECK: casah w0, w1, [x2]
17 # CHECK: caslh w0, w1, [x2]
18 # CHECK: casalh w0, w1, [x2]
28 # CHECK: cas w0, w1, [x2]
29 # CHECK: casa w0, w1, [x2]
[all …]
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| /external/llvm/test/CodeGen/MIR/AArch64/ |
| D | machine-dead-copy.mir | 20 liveins: %w0, %w1
22 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
23 RET_ReallyLR implicit %w0
35 liveins: %w0, %w1
37 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
38 %w0 = COPY %w20
39 RET_ReallyLR implicit %w0
50 liveins: %w0, %w1
52 BL @foo, csr_aarch64_aapcs, implicit %w0, implicit-def %w0
53 %w20 = COPY %w0
[all …]
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| /external/libunwind/src/sh/ |
| D | Gis_signal_frame.c | 71 unw_word_t w0, ip; in unw_is_signal_frame() local
83 ret = (*a->access_mem) (as, ip, &w0, 0, arg); in unw_is_signal_frame()
87 if (w0 != 0xc3109305) in unw_is_signal_frame()
90 ret = (*a->access_mem) (as, ip+4, &w0, 0, arg); in unw_is_signal_frame()
94 if (w0 != 0x200b200b) in unw_is_signal_frame()
97 ret = (*a->access_mem) (as, ip+8, &w0, 0, arg); in unw_is_signal_frame()
101 if (w0 != 0x200b200b) in unw_is_signal_frame()
104 ret = (*a->access_mem) (as, ip+12, &w0, 0, arg); in unw_is_signal_frame()
108 if (w0 == 0x0077200b) in unw_is_signal_frame()
110 else if (w0 == 0x00ad200b) in unw_is_signal_frame()
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| /external/llvm/test/MC/Mips/msa/ |
| D | test_cbranch.s | 3 #CHECK: bnz.b $w0, 4 # encoding: [0x47,0x80,0x00,0x01]
10 #CHECK: bnz.b $w0, SYMBOL0 # encoding: [0x47,0x80,A,A]
23 #CHECK: bnz.v $w0, 4 # encoding: [0x45,0xe0,0x00,0x01]
25 #CHECK: bnz.v $w0, SYMBOL0 # encoding: [0x45,0xe0,A,A]
29 #CHECK: bz.b $w0, 128 # encoding: [0x47,0x00,0x00,0x20]
37 #CHECK: bz.b $w0, SYMBOL0 # encoding: [0x47,0x00,A,A]
50 #CHECK: bz.v $w0, 4 # encoding: [0x45,0x60,0x00,0x01]
52 #CHECK: bz.v $w0, SYMBOL0 # encoding: [0x45,0x60,A,A]
56 bnz.b $w0, 4
60 bnz.b $w0, SYMBOL0
[all …]
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| /external/libunwind/src/arm/ |
| D | Gis_signal_frame.c | 56 unw_word_t w0, ip; in unw_is_signal_frame() local
68 if ((ret = (*a->access_mem) (as, ip, &w0, 0, arg)) < 0) in unw_is_signal_frame()
74 if (w0 == MOV_R7_SIGRETURN || w0 == ARM_SIGRETURN || w0 == THUMB_SIGRETURN) in unw_is_signal_frame()
77 else if (w0 == MOV_R7_RT_SIGRETURN || w0 == ARM_RT_SIGRETURN in unw_is_signal_frame()
78 || w0 == THUMB_RT_SIGRETURN) in unw_is_signal_frame()
|
| /external/vixl/test/aarch64/ |
| D | test-abi.cc | 50 VIXL_CHECK(abi.GetReturnGenericOperand<bool>().Equals(GenericOperand(w0))); in TEST()
51 VIXL_CHECK(abi.GetReturnGenericOperand<char>().Equals(GenericOperand(w0))); in TEST()
52 VIXL_CHECK(abi.GetReturnGenericOperand<int8_t>().Equals(GenericOperand(w0))); in TEST()
53 VIXL_CHECK(abi.GetReturnGenericOperand<uint8_t>().Equals(GenericOperand(w0))); in TEST()
56 GenericOperand(w0))); in TEST()
57 VIXL_CHECK(abi.GetReturnGenericOperand<int16_t>().Equals(GenericOperand(w0))); in TEST()
59 abi.GetReturnGenericOperand<uint16_t>().Equals(GenericOperand(w0))); in TEST()
60 VIXL_CHECK(abi.GetReturnGenericOperand<int>().Equals(GenericOperand(w0))); in TEST()
61 VIXL_CHECK(abi.GetReturnGenericOperand<int32_t>().Equals(GenericOperand(w0))); in TEST()
63 abi.GetReturnGenericOperand<uint32_t>().Equals(GenericOperand(w0))); in TEST()
[all …]
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| /external/freetype/src/autofit/ |
| D | afwarp.c | 259 warper->w0 = warper->x2 - warper->x1; in af_warper_compute()
261 if ( warper->w0 <= 64 ) in af_warper_compute()
277 if ( warper->w0 <= 128 ) in af_warper_compute()
280 if ( warper->w0 <= 96 ) in af_warper_compute()
284 if ( warper->wmin < warper->w0 - margin ) in af_warper_compute()
285 warper->wmin = warper->w0 - margin; in af_warper_compute()
287 if ( warper->wmax > warper->w0 + margin ) in af_warper_compute()
288 warper->wmax = warper->w0 + margin; in af_warper_compute()
291 if ( warper->wmin < warper->w0 * 3 / 4 ) in af_warper_compute()
292 warper->wmin = warper->w0 * 3 / 4; in af_warper_compute()
[all …]
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