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Searched refs:i32 (Results 1 – 25 of 108) sorted by relevance

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/frameworks/rs/driver/runtime/ll32/
D	allocation.ll	1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v… 4 declare i8* @rsOffset([1 x i32] %a.coerce, i32 %sizeOf, i32 %x, i32 %y, i32 %z) 5 declare i8* @rsOffsetNs([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) 36 define void @rsSetElementAtImpl_char([1 x i32] %a.coerce, i8 signext %val, i32 %x, i32 %y, i32 %z) … 37 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 42 define signext i8 @rsGetElementAtImpl_char([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { 43 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 1, i32 %x, i32 %y, i32 %z) #2 49 define void @rsSetElementAtImpl_char2([1 x i32] %a.coerce, <2 x i8> %val, i32 %x, i32 %y, i32 %z) #… 50 %1 = tail call i8* @rsOffset([1 x i32] %a.coerce, i32 2, i32 %x, i32 %y, i32 %z) #2 56 define <2 x i8> @rsGetElementAtImpl_char2([1 x i32] %a.coerce, i32 %x, i32 %y, i32 %z) #0 { [all …]
/frameworks/rs/driver/runtime/ll64/
D	allocation.ll	6 …re i8* @rsOffset(%struct.rs_allocation* nocapture readonly %a, i32 %sizeOf, i32 %x, i32 %y, i32 %z) 7 declare i8* @rsOffsetNs(%struct.rs_allocation* nocapture readonly %a, i32 %x, i32 %y, i32 %z) 38 …pl_char(%struct.rs_allocation* nocapture readonly %a, i8 signext %val, i32 %x, i32 %y, i32 %z) #1 { 39 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 1, i32 %x, i32 %y, i32 %z) #2 44 …@rsGetElementAtImpl_char(%struct.rs_allocation* nocapture readonly %a, i32 %x, i32 %y, i32 %z) #0 { 45 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 1, i32 %x, i32 %y, i32 %z) #2 51 …ntAtImpl_char2(%struct.rs_allocation* nocapture readonly %a, i16 %val, i32 %x, i32 %y, i32 %z) #1 { 52 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 2, i32 %x, i32 %y, i32 %z) #2 59 …rsGetElementAtImpl_char2(%struct.rs_allocation* nocapture readonly %a, i32 %x, i32 %y, i32 %z) #0 { 60 %1 = tail call i8* @rsOffset(%struct.rs_allocation* %a, i32 2, i32 %x, i32 %y, i32 %z) #2 [all …]
/frameworks/compile/libbcc/tests/libbcc/
D	test_reduce_general_cleanup.ll	27 %struct.IndexedVal = type { float, i32 } 29 @.rs.reduce_fn.aiAccum = global i8* bitcast (void (i32, i32) @aiAccum to i8), align 4 33 @.rs.reduce_fn.fMMAccumulator = global i8 bitcast (void (%struct.MinAndMax, float, i32) @fMMAccu… 35 @.rs.reduce_fn.fMMOutConverter = global i8* bitcast (void (<2 x i32>, %struct.MinAndMax)* @fMMOut… 36 @.rs.reduce_fn.fzInit = global i8* bitcast (void (i32) @fzInit to i8), align 4 37 @.rs.reduce_fn.fzAccum = global i8 bitcast (void (i32, i32, i32) @fzAccum to i8), align 4 38 @.rs.reduce_fn.fzCombine = global i8 bitcast (void (i32, i32)* @fzCombine to i8), align 4 39 @.rs.reduce_fn.fz2Init = global i8 bitcast (void (<2 x i32>) @fz2Init to i8), align 4 40 @.rs.reduce_fn.fz2Accum = global i8 bitcast (void (<2 x i32>, i32, i32, i32) @fz2Accum to i8), … 41 @.rs.reduce_fn.fz2Combine = global i8 bitcast (void (<2 x i32>, <2 x i32>)* @fz2Combine to i8*),… [all …]
D	test_reduce_general_metadata.ll	43 %struct.IndexedVal.1 = type { float, i32 } 45 ….0 { %struct.IndexedVal.1 { float 0.000000e+00, i32 -1 }, %struct.IndexedVal.1 { float -0.000000e+… 46 …i32>) @fz2Init to i8), i8 bitcast (void ([256 x i32], [256 x i32])* @hsgCombine to i8), i8… 49 define internal void @aiAccum(i32* nocapture %accum, i32 %val) #0 { 50 %1 = load i32, i32* %accum, align 4, !tbaa !18 51 %2 = add nsw i32 %1, %val 52 store i32 %2, i32* %accum, align 4, !tbaa !18 57 define internal void @mpyInit(i32* nocapture %accum) #0 { 58 store i32 1, i32* %accum, align 4, !tbaa !18 63 define internal void @mpyAccum(i32* nocapture %accum, i32 %val) #0 { [all …]
D	getelementptr.ll	24 define void @root(i32* nocapture %ain, i32* nocapture %out, i32 %x, i32 %y, i32 %z) { 26 ; CHECK: define void @root.expand(%RsExpandKernelDriverInfoPfx* %p, i32 %x1, i32 %x2, i32 %outstep) 28 …entptr inbounds %RsExpandKernelDriverInfoPfx, %RsExpandKernelDriverInfoPfx* %p, i32 0, i32 1, i32 0 29 ; CHECK: load i32, i32* %instep_addr.gep 30 …entptr inbounds %RsExpandKernelDriverInfoPfx, %RsExpandKernelDriverInfoPfx* %p, i32 0, i32 0, i32 0 32 …entptr inbounds %RsExpandKernelDriverInfoPfx, %RsExpandKernelDriverInfoPfx* %p, i32 0, i32 3, i32 0 34 …entptr inbounds %RsExpandKernelDriverInfoPfx, %RsExpandKernelDriverInfoPfx* %p, i32 0, i32 7, i32 1 35 ; CHECK: load i32, i32* %Y.gep 36 …entptr inbounds %RsExpandKernelDriverInfoPfx, %RsExpandKernelDriverInfoPfx* %p, i32 0, i32 7, i32 2 37 ; CHECK: load i32, i32* %Z.gep [all …]
/frameworks/rs/driver/runtime/arch/
D	neon.ll	1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v… 10 declare <2 x i32> @llvm.arm.neon.vmaxs.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 11 declare <4 x i32> @llvm.arm.neon.vmaxs.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 12 declare <2 x i32> @llvm.arm.neon.vmaxu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 13 declare <4 x i32> @llvm.arm.neon.vmaxu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 19 declare <2 x i32> @llvm.arm.neon.vmins.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 20 declare <4 x i32> @llvm.arm.neon.vmins.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 21 declare <2 x i32> @llvm.arm.neon.vminu.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 22 declare <4 x i32> @llvm.arm.neon.vminu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 27 declare <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32>, <4 x i32>) nounwind readnone [all …]
D	asimd.ll	10 declare <2 x i32> @llvm.aarch64.neon.smax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 11 declare <4 x i32> @llvm.aarch64.neon.smax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 12 declare <2 x i32> @llvm.aarch64.neon.umax.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 13 declare <4 x i32> @llvm.aarch64.neon.umax.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 19 declare <2 x i32> @llvm.aarch64.neon.smin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 20 declare <4 x i32> @llvm.aarch64.neon.smin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 21 declare <2 x i32> @llvm.aarch64.neon.umin.v2i32(<2 x i32>, <2 x i32>) nounwind readnone 22 declare <4 x i32> @llvm.aarch64.neon.umin.v4i32(<4 x i32>, <4 x i32>) nounwind readnone 27 declare <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i32>, <4 x i32>) nounwind readnone 28 declare <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i64>, <2 x i64>) nounwind readnone [all …]
D	x86_sse2.ll	1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v… 24 %1 = shufflevector <3 x float> %in, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 25 %2 = shufflevector <3 x float> %low, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 26 %3 = shufflevector <3 x float> %high, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 28 %5 = shufflevector <4 x float> %4, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> 33 %1 = shufflevector <2 x float> %in, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 34 %2 = shufflevector <2 x float> %low, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 35 %3 = shufflevector <2 x float> %high, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 37 %5 = shufflevector <4 x float> %4, <4 x float> undef, <2 x i32> <i32 0, i32 1> 42 %1 = insertelement <4 x float> undef, float %in, i32 0 [all …]
D	x86_sse3.ll	1 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v… 4 declare <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64>, i32) nounwind readnone 12 %4 = extractelement <4 x float> %3, i32 0 18 %2 = shufflevector <3 x float> %1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 20 %4 = tail call <2 x i64> @llvm.x86.sse2.psll.dq(<2 x i64> %3, i32 32) 24 %8 = extractelement <4 x float> %7, i32 0 30 %2 = shufflevector <2 x float> %1, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> 32 %4 = extractelement <4 x float> %3, i32 0 45 %4 = extractelement <4 x float> %3, i32 0 52 %2 = shufflevector <3 x float> %1, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> [all …]
/frameworks/av/media/libstagefright/foundation/tests/
D	Flagged_test.cpp	208 using i32 = int32_t; in TEST_F() typedef 213 static_assert(Flagged<i32, u32, 0u, 0u, 0>::sFlagMask == 0u, ""); in TEST_F() 214 static_assert(Flagged<i32, u32, 0u, 0u, 0>::sFlagShift == 0, ""); in TEST_F() 215 static_assert(Flagged<i32, u32, 0u, 0u, 0>::sEffectiveMask == 0u, ""); in TEST_F() 217 static_assert(Flagged<i32, u32, 0u, 0u, 10>::sFlagMask == 0u, ""); in TEST_F() 218 static_assert(Flagged<i32, u32, 0u, 0u, 10>::sFlagShift == 10, ""); in TEST_F() 219 static_assert(Flagged<i32, u32, 0u, 0u, 10>::sEffectiveMask == 0u, ""); in TEST_F() 221 static_assert(Flagged<i32, u32, 0u, 0u, -1>::sFlagMask == 0u, ""); in TEST_F() 222 static_assert(Flagged<i32, u32, 0u, 0u, -1>::sFlagShift == 0, ""); in TEST_F() 223 static_assert(Flagged<i32, u32, 0u, 0u, -1>::sEffectiveMask == 0u, ""); in TEST_F() [all …]
/frameworks/rs/rsov/compiler/tests/rs_allocation/
D	access_same.ll	12 %struct.rs_allocation = type { i32* } 20 %0 = extractelement <4 x i8> %in, i32 0 21 %conv = zext i8 %0 to i32 22 %1 = extractelement <4 x i8> %in, i32 1 23 %conv1 = zext i8 %1 to i32 24 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @a1 to i32*), align 4 25 %2 = insertvalue [1 x i32] undef, i32 %.unpack, 0 26 …l call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i32 %conv1) #2 27 %3 = extractelement <4 x i8> %in, i32 2 28 %conv2 = zext i8 %3 to i32 [all …]
D	multi_read.ll	12 %struct.rs_allocation = type { i32* } 21 %0 = extractelement <4 x i8> %in, i32 0 22 %conv = zext i8 %0 to i32 23 %1 = extractelement <4 x i8> %in, i32 1 24 %conv1 = zext i8 %1 to i32 25 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @a1 to i32*), align 4 26 %2 = insertvalue [1 x i32] undef, i32 %.unpack, 0 27 …l call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i32 %conv1) #2 28 %3 = extractelement <4 x i8> %in, i32 2 29 %conv2 = zext i8 %3 to i32 [all …]
D	read_write.ll	12 %struct.rs_allocation = type { i32* } 19 define <4 x i8> @k1(<4 x i8> %in, i32 %x, i32 %y) #0 { 21 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @r to i32), align 4 22 %0 = insertvalue [1 x i32] undef, i32 %.unpack, 0 23 …%call = tail call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %0, i32 %x, i32 %… 25 %splat.splatinsert = insertelement <4 x i8> undef, i8 %1, i32 0 26 …%splat.splat = shufflevector <4 x i8> %splat.splatinsert, <4 x i8> undef, <4 x i32> zeroinitializer 29 %.unpack6 = load i32, i32 bitcast (%struct.rs_allocation* @w to i32*), align 4 30 %2 = insertvalue [1 x i32] undef, i32 %.unpack6, 0 31 …oid @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32] %2, <4 x i8> %add1, i32 %x, i32 %y)… [all …]
D	read.ll	12 %struct.rs_allocation = type { i32* } 20 %0 = extractelement <4 x i8> %in, i32 0 21 %conv = zext i8 %0 to i32 22 %1 = extractelement <4 x i8> %in, i32 1 23 %conv1 = zext i8 %1 to i32 24 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @alloc to i32*), align 4 25 %2 = insertvalue [1 x i32] undef, i32 %.unpack, 0 26 …l call <4 x i8> @_Z21rsGetElementAt_uchar413rs_allocationjj([1 x i32] %2, i32 %conv, i32 %conv1) #2 28 %conv2 = zext i8 %3 to i32 29 %4 = extractelement <4 x i8> %call, i32 2 [all …]
D	write.ll	12 %struct.rs_allocation = type { i32* } 18 define <4 x i8> @k1(<4 x i8> %in, i32 %x, i32 %y) #0 { 21 %splat.splatinsert = insertelement <4 x i8> undef, i8 %0, i32 0 22 …%splat.splat = shufflevector <4 x i8> %splat.splatinsert, <4 x i8> undef, <4 x i32> zeroinitializer 24 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @alloc to i32*), align 4 25 %1 = insertvalue [1 x i32] undef, i32 %.unpack, 0 26 …void @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32] %1, <4 x i8> %add, i32 %x, i32 %y)… 30 declare void @_Z21rsSetElementAt_uchar413rs_allocationDv4_hjj([1 x i32], <4 x i8>, i32, i32) #1 53 !0 = !{i32 1, !"wchar_size", i32 4} 54 !1 = !{i32 1, !"min_enum_size", i32 4}
D	rewrite_getdim.ll	20 %struct.rs_allocation = type { i32* } 31 define i32 @getDim(i32 %dummy) local_unnamed_addr #0 { 33 %.unpack = load i32, i32* bitcast (%struct.rs_allocation* @g to i32*), align 4 34 %0 = insertvalue [1 x i32] undef, i32 %.unpack, 0 35 %call = tail call i32 @_Z19rsAllocationGetDimX13rs_allocation([1 x i32] %0) #2 36 ret i32 %call 39 declare i32 @_Z19rsAllocationGetDimX13rs_allocation([1 x i32]) local_unnamed_addr #1 62 !0 = !{i32 1, !"wchar_size", i32 4} 63 !1 = !{i32 1, !"min_enum_size", i32 4}
D	copy_coords.ll	`11 define <4 x i8> @copy_coords(<4 x i8> %in, i32 %x, i32 %y) #0 { 13 %conv = trunc i32 %x to i8 14 %0 = insertelement <4 x i8> %in, i8 %conv, i32 0 15 %conv1 = trunc i32 %y to i8 16 %1 = insertelement <4 x i8> %0, i8 %conv1, i32 1 28 !0 = !{i32 1, !"wchar_size", i32 4} 29 !1 = !{i32 1, !"min_enum_size", i32 4}`
/frameworks/rs/rsov/compiler/tests/single_kernel/
D	duff.ll	`10 define i32 @duff(i32 %count) #0 { 12 %add = add nsw i32 %count, 7 13 %div = sdiv i32 %add, 8 14 %rem = srem i32 %count, 8 15 switch i32 %rem, label %sw.epilog [ 16 i32 0, label %do.body 17 i32 7, label %sw.bb1 18 i32 6, label %sw.bb2 19 i32 5, label %sw.bb3 20 i32 4, label %sw.bb6 [all …]`
D	fib.ll	`9 define i32 @fib(i32 %n) #0 { 11 %n.off8 = add i32 %n, -1 12 %0 = icmp ult i32 %n.off8, 2 16 %n.tr10 = phi i32 [ %sub2, %if.end ], [ %n, %entry ] 17 %accumulator.tr9 = phi i32 [ %add, %if.end ], [ 1, %entry ] 18 %sub = add nsw i32 %n.tr10, -1 19 %call = tail call i32 @fib(i32 %sub) 20 %sub2 = add nsw i32 %n.tr10, -2 21 %add = add nsw i32 %call, %accumulator.tr9 22 %n.off = add i32 %n.tr10, -3 [all …]`
/frameworks/av/media/libstagefright/codecs/on2/h264dec/source/
D	h264bsd_reconstruct.h	`74 i32 x0, 75 i32 y0, 85 i32 x0, 86 i32 y0, 96 i32 x0, 97 i32 y0, 107 i32 x0, 108 i32 y0, 119 i32 x0, 120 i32 y0, [all …]`
D	h264bsd_reconstruct.c	`113 i32 x0, in h264bsdInterpolateChromaHor() 114 i32 y0, in h264bsdInterpolateChromaHor() 209 i32 x0, in h264bsdInterpolateChromaVer() 210 i32 y0, in h264bsdInterpolateChromaVer() 305 i32 x0, in h264bsdInterpolateChromaHorVer() 306 i32 y0, in h264bsdInterpolateChromaHorVer() 429 i32 xInt, yInt; in PredictChroma() 494 i32 x0, in h264bsdInterpolateVerHalf() 495 i32 y0, in h264bsdInterpolateVerHalf() 503 i32 tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, tmp7; in h264bsdInterpolateVerHalf() [all …]`
/frameworks/rs/rsov/compiler/tests/image/
D	blend.ll	17 define <4 x i8> @setImageAlpha(<4 x i8> %in, i32 %x, i32 %y) #0 { 19 %call = tail call <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8> %in) #2 21 %conv = zext i8 %0 to i32 22 %splat.splatinsert = insertelement <4 x i32> undef, i32 %conv, i32 0 23 …%splat.splat = shufflevector <4 x i32> %splat.splatinsert, <4 x i32> undef, <4 x i32> zeroinitiali… 24 %mul = mul <4 x i32> %splat.splat, %call 25 %shr = lshr <4 x i32> %mul, <i32 8, i32 8, i32 8, i32 8> 26 %call1 = tail call <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32> %shr) #2 27 %1 = insertelement <4 x i8> %call1, i8 %0, i32 3 32 declare <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32>) #1 [all …]
D	contrast.ll	39 %0 = shufflevector <4 x i8> %in, <4 x i8> undef, <3 x i32> <i32 0, i32 1, i32 2> 42 %splat.splatinsert = insertelement <3 x float> undef, float %1, i32 0 43 …%splat.splat = shufflevector <3 x float> %splat.splatinsert, <3 x float> undef, <3 x i32> zeroinit… 46 %splat.splatinsert1 = insertelement <3 x float> undef, float %2, i32 0 47 …%splat.splat2 = shufflevector <3 x float> %splat.splatinsert1, <3 x float> undef, <3 x i32> zeroin… 51 %3 = shufflevector <3 x i8> %call5, <3 x i8> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 undef> 52 %4 = insertelement <4 x i8> %3, i8 -1, i32 3 68 %1 = getelementptr inbounds { float }, { float }* %0, i32 0, i32 0 87 !0 = !{i32 1, !"wchar_size", i32 4} 88 !1 = !{i32 1, !"min_enum_size", i32 4}
/frameworks/rs/rsov/compiler/tests/arguments/
D	signedness.ll	`84 define <4 x i32> @increment4(<4 x i32> %in) local_unnamed_addr #0 { 86 %add = add <4 x i32> %in, <i32 1, i32 1, i32 1, i32 1> 87 ret <4 x i32> %add 91 define <4 x i32> @uincrement4(<4 x i32> %in) local_unnamed_addr #0 { 93 %add = add <4 x i32> %in, <i32 1, i32 1, i32 1, i32 1> 94 ret <4 x i32> %add 98 define i32 @increment(i32 %in) local_unnamed_addr #0 { 100 %add = add nsw i32 %in, 1 101 ret i32 %add 105 define i32 @uincrement(i32 %in) local_unnamed_addr #0 { [all …]`
/frameworks/rs/rsov/compiler/tests/multi_function/
D	blend_mf.ll	25 %call = tail call <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8> %in) #2 26 %mul = mul <4 x i32> %call, <i32 37, i32 37, i32 37, i32 37> 27 %shr = lshr <4 x i32> %mul, <i32 8, i32 8, i32 8, i32 8> 28 %call1 = tail call <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32> %shr) #2 30 %0 = insertelement <4 x i8> %call2, i8 37, i32 3 42 declare <4 x i8> @_Z14convert_uchar4Dv4_j(<4 x i32>) #1 45 declare <4 x i32> @_Z13convert_uint4Dv4_h(<4 x i8>) #1 58 !0 = !{i32 1, !"wchar_size", i32 4} 59 !1 = !{i32 1, !"min_enum_size", i32 4}

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