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Searched refs:SU (Results 1 – 25 of 155) sorted by relevance

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/external/llvm/lib/Target/Hexagon/
DHexagonMachineScheduler.cpp43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) { in isResourceAvailable() argument
44 if (!SU || !SU->getInstr()) in isResourceAvailable()
49 switch (SU->getInstr()->getOpcode()) { in isResourceAvailable()
51 if (!ResourcesModel->canReserveResources(*SU->getInstr())) in isResourceAvailable()
75 if (I->getSUnit() == SU) in isResourceAvailable()
83 bool VLIWResourceModel::reserveResources(SUnit *SU) { in reserveResources() argument
86 if (!SU) { in reserveResources()
94 if (!isResourceAvailable(SU)) { in reserveResources()
101 switch (SU->getInstr()->getOpcode()) { in reserveResources()
103 ResourcesModel->reserveResources(*SU->getInstr()); in reserveResources()
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/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) { in numberRCValPredInSU() argument
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberRCValPredInSU()
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU, in numberRCValSuccInSU() argument
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberRCValSuccInSU()
145 static unsigned numberCtrlDepsInSU(SUnit *SU) { in numberCtrlDepsInSU() argument
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in numberCtrlDepsInSU()
155 static unsigned numberCtrlPredInSU(SUnit *SU) { in numberCtrlPredInSU() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in numberCtrlPredInSU()
173 SUnit *SU = &(*SUnits)[i]; in initNodes() local
174 initNumRegDefsLeft(SU); in initNodes()
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DScheduleDAGRRList.cpp186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
187 return Topo.IsReachable(SU, TargetSU); in IsReachable()
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
193 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
199 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
200 Topo.AddPred(SU, D.getSUnit()); in AddPred()
201 SU->addPred(D); in AddPred()
207 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
208 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
209 SU->removePred(D); in RemovePred()
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DScheduleDAGSDNodes.cpp78 SUnit *SU = &SUnits.back(); in newSUnit() local
83 SU->SchedulingPref = Sched::None; in newSUnit()
85 SU->SchedulingPref = TLI.getSchedulingPreference(N); in newSUnit()
86 return SU; in newSUnit()
90 SUnit *SU = newSUnit(Old->getNode()); in Clone() local
91 SU->OrigNode = Old->OrigNode; in Clone()
92 SU->Latency = Old->Latency; in Clone()
93 SU->isVRegCycle = Old->isVRegCycle; in Clone()
94 SU->isCall = Old->isCall; in Clone()
95 SU->isCallOp = Old->isCallOp; in Clone()
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DScheduleDAGFast.cpp88 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
89 SU->addPred(D); in AddPred()
94 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
95 SU->removePred(D); in RemovePred()
99 void ReleasePred(SUnit *SU, SDep *PredEdge);
100 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
140 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
161 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { in ReleasePredecessors() argument
163 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
165 ReleasePred(SU, &*I); in ReleasePredecessors()
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DScheduleDAGVLIW.cpp87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) { in releaseSucc() argument
131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in releaseSucc()
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
147 releaseSucc(SU, *I); in releaseSuccessors()
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { in scheduleNodeTopDown() argument
156 DEBUG(SU->dump(this)); in scheduleNodeTopDown()
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/external/llvm/test/CodeGen/AArch64/
Daarch64-stp-cluster.ll6 ; CHECK:Cluster ld/st SU(4) - SU(3)
7 ; CHECK:Cluster ld/st SU(2) - SU(5)
8 ; CHECK:SU(4): STRXui %vreg1, %vreg0, 1
9 ; CHECK:SU(3): STRXui %vreg1, %vreg0, 2
10 ; CHECK:SU(2): STRXui %vreg1, %vreg0, 3
11 ; CHECK:SU(5): STRXui %vreg1, %vreg0, 4
27 ; CHECK:Cluster ld/st SU(4) - SU(3)
28 ; CHECK:Cluster ld/st SU(2) - SU(5)
29 ; CHECK:SU(4): STRWui %vreg1, %vreg0, 1
30 ; CHECK:SU(3): STRWui %vreg1, %vreg0, 2
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Darm64-ldp-cluster.ll8 ; CHECK: Cluster ld/st SU(1) - SU(2)
9 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
10 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
13 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
14 ; EXYNOS: SU(1): %vreg{{[0-9]+}}<def> = LDRWui
15 ; EXYNOS: SU(2): %vreg{{[0-9]+}}<def> = LDRWui
28 ; CHECK: Cluster ld/st SU(1) - SU(2)
29 ; CHECK: SU(1): %vreg{{[0-9]+}}<def> = LDRSWui
30 ; CHECK: SU(2): %vreg{{[0-9]+}}<def> = LDRSWui
33 ; EXYNOS: Cluster ld/st SU(1) - SU(2)
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/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DScheduleDAGRRList.cpp190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) { in IsReachable() argument
191 return Topo.IsReachable(SU, TargetSU); in IsReachable()
196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) { in WillCreateCycle() argument
197 return Topo.WillCreateCycle(SU, TargetSU); in WillCreateCycle()
203 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
204 Topo.AddPred(SU, D.getSUnit()); in AddPred()
205 SU->addPred(D); in AddPred()
211 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
212 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
213 SU->removePred(D); in RemovePred()
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DScheduleDAGFast.cpp82 void AddPred(SUnit *SU, const SDep &D) { in AddPred() argument
83 SU->addPred(D); in AddPred()
88 void RemovePred(SUnit *SU, const SDep &D) { in RemovePred() argument
89 SU->removePred(D); in RemovePred()
93 void ReleasePred(SUnit *SU, SDep *PredEdge);
94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
134 void ScheduleDAGFast::ReleasePred(SUnit *SU, SDep *PredEdge) { in ReleasePred() argument
155 void ScheduleDAGFast::ReleasePredecessors(SUnit *SU, unsigned CurCycle) { in ReleasePredecessors() argument
157 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in ReleasePredecessors()
159 ReleasePred(SU, &*I); in ReleasePredecessors()
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DScheduleDAGSDNodes.cpp70 SUnit *SU = &SUnits.back(); in NewSUnit() local
75 SU->SchedulingPref = Sched::None; in NewSUnit()
77 SU->SchedulingPref = TLI.getSchedulingPreference(N); in NewSUnit()
78 return SU; in NewSUnit()
82 SUnit *SU = NewSUnit(Old->getNode()); in Clone() local
83 SU->OrigNode = Old->OrigNode; in Clone()
84 SU->Latency = Old->Latency; in Clone()
85 SU->isVRegCycle = Old->isVRegCycle; in Clone()
86 SU->isCall = Old->isCall; in Clone()
87 SU->isCallOp = Old->isCallOp; in Clone()
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DScheduleDAGList.cpp81 void ReleaseSucc(SUnit *SU, const SDep &D);
82 void ReleaseSuccessors(SUnit *SU);
83 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
108 void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) { in ReleaseSucc() argument
121 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency()); in ReleaseSucc()
129 void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) { in ReleaseSuccessors() argument
131 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ReleaseSuccessors()
136 ReleaseSucc(SU, *I); in ReleaseSuccessors()
143 void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle) { in ScheduleNodeTopDown() argument
145 DEBUG(SU->dump(this)); in ScheduleNodeTopDown()
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/external/llvm/lib/CodeGen/
DMachineScheduler.cpp554 void ScheduleDAGMI::releaseSucc(SUnit *SU, SDep *SuccEdge) { in releaseSucc() argument
573 if (SuccSU->TopReadyCycle < SU->TopReadyCycle + SuccEdge->getLatency()) in releaseSucc()
574 SuccSU->TopReadyCycle = SU->TopReadyCycle + SuccEdge->getLatency(); in releaseSucc()
582 void ScheduleDAGMI::releaseSuccessors(SUnit *SU) { in releaseSuccessors() argument
583 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in releaseSuccessors()
585 releaseSucc(SU, &*I); in releaseSuccessors()
593 void ScheduleDAGMI::releasePred(SUnit *SU, SDep *PredEdge) { in releasePred() argument
612 if (PredSU->BotReadyCycle < SU->BotReadyCycle + PredEdge->getLatency()) in releasePred()
613 PredSU->BotReadyCycle = SU->BotReadyCycle + PredEdge->getLatency(); in releasePred()
621 void ScheduleDAGMI::releasePredecessors(SUnit *SU) { in releasePredecessors() argument
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DScheduleDAGInstrs.cpp283 void ScheduleDAGInstrs::addPhysRegDataDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDataDeps() argument
284 const MachineOperand &MO = SU->getInstr()->getOperand(OperIdx); in addPhysRegDataDeps()
295 SUnit *UseSU = I->SU; in addPhysRegDataDeps()
296 if (UseSU == SU) in addPhysRegDataDeps()
305 Dep = SDep(SU, SDep::Artificial); in addPhysRegDataDeps()
309 SU->hasPhysRegDefs = true; in addPhysRegDataDeps()
310 Dep = SDep(SU, SDep::Data, *Alias); in addPhysRegDataDeps()
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse, in addPhysRegDataDeps()
317 ST.adjustSchedDependency(SU, UseSU, Dep); in addPhysRegDataDeps()
326 void ScheduleDAGInstrs::addPhysRegDeps(SUnit *SU, unsigned OperIdx) { in addPhysRegDeps() argument
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DLatencyPriorityQueue.cpp56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { in getSingleUnscheduledPred() argument
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in getSingleUnscheduledPred()
73 void LatencyPriorityQueue::push(SUnit *SU) { in push() argument
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in push()
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; in push()
84 Queue.push_back(SU); in push()
92 void LatencyPriorityQueue::scheduledNode(SUnit *SU) { in scheduledNode() argument
93 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in scheduledNode()
105 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) { in AdjustPriorityOfUnscheduledPreds() argument
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/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp58 SUnit *SU = nullptr; in pickNode() local
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) || in pickNode()
101 SU = pickAlu(); in pickNode()
102 if (!SU && !PhysicalRegCopy.empty()) { in pickNode()
103 SU = PhysicalRegCopy.front(); in pickNode()
106 if (SU) { in pickNode()
113 if (!SU) { in pickNode()
115 SU = pickOther(IDFetch); in pickNode()
116 if (SU) in pickNode()
121 if (!SU) { in pickNode()
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DSIMachineScheduler.cpp178 void SIScheduleBlock::addUnit(SUnit *SU) { in addUnit() argument
179 NodeNum2Index[SU->NodeNum] = SUnits.size(); in addUnit()
180 SUnits.push_back(SU); in addUnit()
187 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); in traceCandidate()
237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) { in tryCandidateTopDown()
245 for (SUnit* SU : TopReadySUs) { in pickNode()
250 TryCand.SU = SU; in pickNode()
251 TopRPTracker.getDownwardPressure(SU->getInstr(), pressure, MaxPressure); in pickNode()
254 TryCand.IsLowLatency = DAG->IsLowLatencySU[SU->NodeNum]; in pickNode()
255 TryCand.LowLatencyOffset = DAG->LowLatencyOffset[SU->NodeNum]; in pickNode()
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/external/swiftshader/third_party/LLVM/lib/CodeGen/
DScheduleDAGInstrs.cpp245 SUnit *SU = NewSUnit(MI); in BuildSchedGraph() local
246 SU->isCall = MCID.isCall(); in BuildSchedGraph()
247 SU->isCommutable = MCID.isCommutable(); in BuildSchedGraph()
251 SU->Latency = 1; in BuildSchedGraph()
253 ComputeLatency(SU); in BuildSchedGraph()
279 if (DefSU != SU && in BuildSchedGraph()
282 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/Reg)); in BuildSchedGraph()
290 if (DefSU != SU && in BuildSchedGraph()
293 DefSU->addPred(SDep(SU, Kind, AOLatency, /*Reg=*/ *Alias)); in BuildSchedGraph()
299 unsigned DataLatency = SU->Latency; in BuildSchedGraph()
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DLatencyPriorityQueue.cpp55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) { in getSingleUnscheduledPred() argument
57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end(); in getSingleUnscheduledPred()
72 void LatencyPriorityQueue::push(SUnit *SU) { in push() argument
76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in push()
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking; in push()
83 Queue.push_back(SU); in push()
91 void LatencyPriorityQueue::ScheduledNode(SUnit *SU) { in ScheduledNode() argument
92 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end(); in ScheduledNode()
104 void LatencyPriorityQueue::AdjustPriorityOfUnscheduledPreds(SUnit *SU) { in AdjustPriorityOfUnscheduledPreds() argument
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DScheduleDAG.cpp56 if (SUnit *SU = Sequence[i]) in dumpSchedule() local
57 SU->dump(this); in dumpSchedule()
173 SUnit *SU = WorkList.pop_back_val(); in setDepthDirty() local
174 SU->isDepthCurrent = false; in setDepthDirty()
175 for (SUnit::const_succ_iterator I = SU->Succs.begin(), in setDepthDirty()
176 E = SU->Succs.end(); I != E; ++I) { in setDepthDirty()
189 SUnit *SU = WorkList.pop_back_val(); in setHeightDirty() local
190 SU->isHeightCurrent = false; in setHeightDirty()
191 for (SUnit::const_pred_iterator I = SU->Preds.begin(), in setHeightDirty()
192 E = SU->Preds.end(); I != E; ++I) { in setHeightDirty()
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/external/llvm/test/CodeGen/ARM/
D2012-06-12-SchedMemLatency.ll8 ; CHECK: SU(2){{.*}}STR{{.*}}Volatile
9 ; CHECK-NOT: ch SU
10 ; CHECK: ch SU(3): Latency=1
11 ; CHECK-NOT: ch SU
12 ; CHECK: SU(3){{.*}}LDR{{.*}}Volatile
13 ; CHECK-NOT: ch SU
14 ; CHECK: ch SU(2): Latency=1
15 ; CHECK-NOT: ch SU
18 ; CHECK: SU(2){{.*}}STR{{.*}}
19 ; CHECK-NOT: ch SU
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/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) { in isLoadAfterStore() argument
28 if (isBCTRAfterSet(SU)) in isLoadAfterStore()
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isLoadAfterStore()
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isLoadAfterStore()
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier()) in isLoadAfterStore()
49 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) { in isBCTRAfterSet() argument
57 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in isBCTRAfterSet()
66 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) { in isBCTRAfterSet()
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/external/llvm/include/llvm/CodeGen/
DScheduleDAGInstrs.h38 SUnit *SU; member
40 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU) in VReg2SUnit()
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {} in VReg2SUnit()
53 unsigned OperandIndex, SUnit *SU) in VReg2SUnitOperIdx()
54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {} in VReg2SUnitOperIdx()
60 SUnit *SU; member
64 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {} in PhysRegSUOper()
194 void addChainDependencies(SUnit *SU, SUList &sus, unsigned Latency) { in addChainDependencies() argument
196 addChainDependency(SU, su, Latency); in addChainDependencies()
200 void addChainDependencies(SUnit *SU, Value2SUsMap &Val2SUsMap);
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DMachineScheduler.h212 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
216 virtual void releaseTopNode(SUnit *SU) = 0;
219 virtual void releaseBottomNode(SUnit *SU) = 0;
332 void updateQueues(SUnit *SU, bool IsTopNode);
346 void releaseSucc(SUnit *SU, SDep *SuccEdge);
347 void releaseSuccessors(SUnit *SU);
348 void releasePred(SUnit *SU, SDep *PredEdge);
349 void releasePredecessors(SUnit *SU);
425 PressureDiff &getPressureDiff(const SUnit *SU) { in getPressureDiff() argument
426 return SUPressureDiffs[SU->NodeNum]; in getPressureDiff()
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DResourcePriorityQueue.h84 void addNode(const SUnit *SU) override { in addNode() argument
88 void updateNode(const SUnit *SU) override {} in updateNode() argument
106 int SUSchedulingCost (SUnit *SU);
110 void initNumRegDefsLeft(SUnit *SU);
111 void updateNumRegDefsLeft(SUnit *SU);
112 int regPressureDelta(SUnit *SU, bool RawPressure = false);
113 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
121 void remove(SUnit *SU) override;
125 bool isResourceAvailable(SUnit *SU);
126 void reserveResources(SUnit *SU);
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