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Searched refs:msr (Results 1 – 25 of 138) sorted by relevance

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/external/llvm/test/MC/AArch64/
Dtrace-regs.s420 msr trcoslar, x28
421 msr trclar, x14
422 msr trcprgctlr, x10
423 msr trcprocselr, x27
424 msr trcconfigr, x24
425 msr trcauxctlr, x8
426 msr trceventctl0r, x16
427 msr trceventctl1r, x27
428 msr trcstallctlr, x26
429 msr trctsctlr, x0
[all …]
Dtrace-regs-diagnostics.s13 msr trcstatr, x0
14 msr trcidr8, x13
15 msr trcidr9, x25
16 msr trcidr10, x2
17 msr trcidr11, x19
18 msr trcidr12, x15
19 msr trcidr13, x24
20 msr trcidr0, x20
21 msr trcidr1, x5
22 msr trcidr2, x18
[all …]
Dgicv3-regs.s116 msr icc_eoir1_el1, x27
117 msr icc_eoir0_el1, x5
118 msr icc_dir_el1, x13
119 msr icc_sgi1r_el1, x21
120 msr icc_asgi1r_el1, x25
121 msr icc_sgi0r_el1, x28
122 msr icc_bpr1_el1, x7
123 msr icc_bpr0_el1, x9
124 msr icc_pmr_el1, x29
125 msr icc_ctlr_el1, x24
[all …]
Darmv8.1a-vhe.s7 msr TTBR1_EL2, x0
8 msr CONTEXTIDR_EL2, x0
9 msr CNTHV_TVAL_EL2, x0
10 msr CNTHV_CVAL_EL2, x0
11 msr CNTHV_CTL_EL2, x0
12 msr SCTLR_EL12, x0
13 msr CPACR_EL12, x0
14 msr TTBR0_EL12, x0
15 msr TTBR1_EL12, x0
16 msr TCR_EL12, x0
[all …]
Darm64-system-encoding.s60 msr ACTLR_EL1, x3
61 msr ACTLR_EL2, x3
62 msr ACTLR_EL3, x3
63 msr AFSR0_EL1, x3
64 msr AFSR0_EL2, x3
65 msr AFSR0_EL3, x3
66 msr AFSR1_EL1, x3
67 msr AFSR1_EL2, x3
68 msr AFSR1_EL3, x3
69 msr AMAIR_EL1, x3
[all …]
Darmv8.2a-statistical-profiling.s8 msr pmblimitr_el1, x0
9 msr pmbptr_el1, x0
10 msr pmbsr_el1, x0
11 msr pmbidr_el1, x0
12 msr pmscr_el2, x0
13 msr pmscr_el12, x0
14 msr pmscr_el1, x0
15 msr pmsicr_el1, x0
16 msr pmsirr_el1, x0
17 msr pmsfcr_el1, x0
[all …]
Dras-extension.s6 msr errselr_el1, x0
7 msr errselr_el1, x15
8 msr errselr_el1, x25
9 msr erxctlr_el1, x1
10 msr erxstatus_el1, x2
11 msr erxaddr_el1, x3
12 msr erxmisc0_el1, x4
13 msr erxmisc1_el1, x5
14 msr disr_el1, x6
15 msr vdisr_el2, x7
[all …]
Dbasic-a64-instructions.s3571 msr spsel, #0
3572 msr daifset, #15
3573 msr daifclr, #12
3702 msr TEECR32_EL1, x12
3703 msr OSDTRRX_EL1, x12
3704 msr MDCCINT_EL1, x12
3705 msr MDSCR_EL1, x12
3706 msr OSDTRTX_EL1, x12
3707 msr DBGDTR_EL0, x12
3708 msr DBGDTRTX_EL0, x12
[all …]
Darmv8.1a-lor.s25 msr LORSA_EL1, x0
26 msr LOREA_EL1, x0
27 msr LORN_EL1, x0
28 msr LORC_EL1, x0
41 msr LORSA_EL1, #0
42 msr LOREA_EL1, #0
43 msr LORN_EL1, #0
44 msr LORC_EL1, #0
45 msr LORID_EL1, x0
Dgicv3-regs-diagnostics.s30 msr icc_iar1_el1, x16
31 msr icc_iar0_el1, x19
32 msr icc_hppir1_el1, x29
33 msr icc_hppir0_el1, x14
34 msr icc_rpr_el1, x6
35 msr ich_vtr_el2, x8
36 msr ich_eisr_el2, x22
37 msr ich_elsr_el2, x8
/external/llvm/test/MC/ARM/
Dmove-banked-regs.s114 msr r8_usr, r2
115 msr r9_usr, r3
116 msr r10_usr, r5
117 msr r11_usr, r7
118 msr r12_usr, r11
119 msr sp_usr, r1
120 msr lr_usr, r2
121 @ CHECK-ARM: msr r8_usr, r2 @ encoding: [0x02,0xf2,0x20,0xe1]
122 @ CHECK-ARM: msr r9_usr, r3 @ encoding: [0x03,0xf2,0x21,0xe1]
123 @ CHECK-ARM: msr r10_usr, r5 @ encoding: [0x05,0xf2,0x22,0xe1]
[all …]
Dthumb2-mclass.s41 msr apsr, r0
42 msr apsr_nzcvq, r0
43 msr iapsr, r0
44 msr iapsr_nzcvq, r0
45 msr eapsr, r0
46 msr eapsr_nzcvq, r0
47 msr xpsr, r0
48 msr xpsr_nzcvq, r0
49 msr ipsr, r0
50 msr epsr, r0
[all …]
Dthumbv7em.s13 msr apsr_g, r0
14 msr apsr_nzcvqg, r0
15 msr iapsr_g, r0
16 msr iapsr_nzcvqg, r0
17 msr eapsr_g, r0
18 msr eapsr_nzcvqg, r0
19 msr xpsr_g, r0
20 msr xpsr_nzcvqg, r0
22 @ CHECK: msr apsr_g, r0 @ encoding: [0x80,0xf3,0x00,0x84]
23 @ CHECK: msr apsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x00,0x8c]
[all …]
/external/llvm/test/MC/Disassembler/AArch64/
Darmv8.1a-vhe.txt30 # CHECK: msr TTBR1_EL2, x0
31 # CHECK: msr CONTEXTIDR_EL2, x0
32 # CHECK: msr CNTHV_TVAL_EL2, x0
33 # CHECK: msr CNTHV_CVAL_EL2, x0
34 # CHECK: msr CNTHV_CTL_EL2, x0
35 # CHECK: msr SCTLR_EL12, x0
36 # CHECK: msr CPACR_EL12, x0
37 # CHECK: msr TTBR0_EL12, x0
38 # CHECK: msr TTBR1_EL12, x0
39 # CHECK: msr TCR_EL12, x0
[all …]
Dtrace-regs.txt405 # CHECK: msr {{trcoslar|TRCOSLAR}}, x28
407 # CHECK: msr {{trclar|TRCLAR}}, x14
409 # CHECK: msr {{trcprgctlr|TRCPRGCTLR}}, x10
411 # CHECK: msr {{trcprocselr|TRCPROCSELR}}, x27
413 # CHECK: msr {{trcconfigr|TRCCONFIGR}}, x24
415 # CHECK: msr {{trcauxctlr|TRCAUXCTLR}}, x8
417 # CHECK: msr {{trceventctl0r|TRCEVENTCTL0R}}, x16
419 # CHECK: msr {{trceventctl1r|TRCEVENTCTL1R}}, x27
421 # CHECK: msr {{trcstallctlr|TRCSTALLCTLR}}, x26
423 # CHECK: msr {{trctsctlr|TRCTSCTLR}}, x0
[all …]
Darmv8.2a-statistical-profiling.txt21 # CHECK: msr PMBLIMITR_EL1, x0
22 # NO_SPE: msr S3_0_C9_C10_0, x0
23 # CHECK: msr PMBPTR_EL1, x0
24 # NO_SPE: msr S3_0_C9_C10_1, x0
25 # CHECK: msr PMBSR_EL1, x0
26 # NO_SPE: msr S3_0_C9_C10_3, x0
27 # CHECK: msr PMBIDR_EL1, x0
28 # NO_SPE: msr S3_0_C9_C10_7, x0
29 # CHECK: msr PMSCR_EL2, x0
30 # NO_SPE: msr S3_4_C9_C9_0, x0
[all …]
Dgicv3-regs.txt117 # CHECK: msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27
119 # CHECK: msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5
121 # CHECK: msr {{icc_dir_el1|ICC_DIR_EL1}}, x13
123 # CHECK: msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21
125 # CHECK: msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25
127 # CHECK: msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28
129 # CHECK: msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7
131 # CHECK: msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9
133 # CHECK: msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29
135 # CHECK: msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dthumb2-mclass.s46 msr apsr, r0
47 msr iapsr, r0
48 msr eapsr, r0
49 msr xpsr, r0
50 msr ipsr, r0
51 msr epsr, r0
52 msr iepsr, r0
53 msr msp, r0
54 msr psp, r0
55 msr primask, r0
[all …]
/external/valgrind/none/tests/arm64/
Dinteger.stdout.exp1239 msr nzcv,x24; ccmp x25,#17,#0x0,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1240 msr nzcv,x24; ccmp x25,#17,#0x1,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1241 msr nzcv,x24; ccmp x25,#17,#0x2,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1242 msr nzcv,x24; ccmp x25,#17,#0x3,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1243 msr nzcv,x24; ccmp x25,#17,#0x4,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1244 msr nzcv,x24; ccmp x25,#17,#0x5,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1245 msr nzcv,x24; ccmp x25,#17,#0x6,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1246 msr nzcv,x24; ccmp x25,#17,#0x7,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1247 msr nzcv,x24; ccmp x25,#17,#0x8,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
1248 msr nzcv,x24; ccmp x25,#17,#0x9,eq; mrs x23,nzcv :: rd 0000000060000000 rm 0000000040000000, rn 000…
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dmove-banked-regs-arm.txt85 @ CHECK: msr r8_usr, r2
86 @ CHECK: msr r9_usr, r3
87 @ CHECK: msr r10_usr, r5
88 @ CHECK: msr r11_usr, r7
89 @ CHECK: msr r12_usr, r11
90 @ CHECK: msr sp_usr, r1
91 @ CHECK: msr lr_usr, r2
101 @ CHECK: msr r8_fiq, r2
102 @ CHECK: msr r9_fiq, r3
103 @ CHECK: msr r10_fiq, r5
[all …]
Dmove-banked-regs-thumb.txt87 @ CHECK: msr r8_usr, r2
88 @ CHECK: msr r9_usr, r3
89 @ CHECK: msr r10_usr, r5
90 @ CHECK: msr r11_usr, r7
91 @ CHECK: msr r12_usr, r11
92 @ CHECK: msr sp_usr, r1
93 @ CHECK: msr lr_usr, r2
103 @ CHECK: msr r8_fiq, r2
104 @ CHECK: msr r9_fiq, r3
105 @ CHECK: msr r10_fiq, r5
[all …]
Dthumb-MSR-MClass.txt42 # CHECK: msr apsr_nzcvq, r0
43 # CHECK: msr apsr_g, r0
44 # CHECK: msr apsr_nzcvqg, r0
50 # CHECK: msr iapsr_nzcvq, r0
51 # CHECK: msr iapsr_g, r0
52 # CHECK: msr iapsr_nzcvqg, r0
58 # CHECK: msr eapsr_nzcvq, r0
59 # CHECK: msr eapsr_g, r0
60 # CHECK: msr eapsr_nzcvqg, r0
66 # CHECK: msr xpsr_nzcvq, r0
[all …]
/external/llvm/test/CodeGen/ARM/
Dspecial-reg-v8m-main.ll93 ; MAINLINE: msr apsr_nzcvqg, r0
94 ; MAINLINE: msr apsr_nzcvq, r0
95 ; MAINLINE: msr apsr_g, r0
96 ; MAINLINE: msr apsr_nzcvqg, r0
97 ; MAINLINE: msr iapsr_nzcvqg, r0
98 ; MAINLINE: msr iapsr_nzcvq, r0
99 ; MAINLINE: msr iapsr_g, r0
100 ; MAINLINE: msr iapsr_nzcvqg, r0
101 ; MAINLINE: msr eapsr_nzcvqg, r0
102 ; MAINLINE: msr eapsr_nzcvq, r0
[all …]
Dspecial-reg-mcore.ll59 ; MCORE: msr apsr_nzcvqg, r0
60 ; MCORE: msr apsr_nzcvq, r0
61 ; MCORE: msr apsr_g, r0
62 ; MCORE: msr apsr_nzcvqg, r0
63 ; MCORE: msr iapsr_nzcvqg, r0
64 ; MCORE: msr iapsr_nzcvq, r0
65 ; MCORE: msr iapsr_g, r0
66 ; MCORE: msr iapsr_nzcvqg, r0
67 ; MCORE: msr eapsr_nzcvqg, r0
68 ; MCORE: msr eapsr_nzcvq, r0
[all …]
Dmsr-it-block.ll19 ; V6M: msr apsr, {{r[0-9]+}}
20 ; V6M: msr apsr, {{r[0-9]+}}
21 ; V7M: msr apsr_nzcvq, {{r[0-9]+}}
22 ; V7M: msr apsr_nzcvq, {{r[0-9]+}}
23 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
24 ; V7A: msr APSR_nzcvqg, {{r[0-9]+}}
40 ; V6M: msr apsr, {{r[0-9]+}}
41 ; V6M: msr apsr, {{r[0-9]+}}
42 ; V7M: msr apsr_nzcvq, {{r[0-9]+}}
43 ; V7M: msr apsr_nzcvq, {{r[0-9]+}}
[all …]

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