Searched refs:IssueWidth (Results 1 – 25 of 41) sorted by relevance
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32 DAG(SchedDAG), IssueWidth(0), IssueCount(0) { in ScoreboardHazardRecognizer()72 IssueWidth = ItinData->SchedModel.IssueWidth; in ScoreboardHazardRecognizer()103 if (IssueWidth == 0) in atIssueLimit()106 return IssueCount == IssueWidth; in atIssueLimit()
63 ResourceLCM = SchedModel.IssueWidth; in init()69 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth; in init()
35 ScheduleHazardRecognizer(), ItinData(II), DAG(SchedDAG), IssueWidth(0), in ScoreboardHazardRecognizer()47 IssueWidth = ItinData->IssueWidth; in ScoreboardHazardRecognizer()101 if (IssueWidth == 0) in atIssueLimit()104 return IssueCount == IssueWidth; in atIssueLimit()
116 unsigned IssueWidth; ///< Max issue per cycle. 0=Unknown. variable121 Itineraries(0), IssueWidth(0) {} in InstrItineraryData()126 IssueWidth(0) {} in InstrItineraryData()
202 InstrItins.IssueWidth = 0; in computeIssueWidth()204 ++InstrItins.IssueWidth; in computeIssueWidth()208 assert(InstrItins.IssueWidth <= 2 && "itinerary bug, too many stage 1 units"); in computeIssueWidth()
52 InstrItins.IssueWidth = 1; in computeIssueWidth()
96 unsigned IssueWidth; variable
94 unsigned getIssueWidth() const { return SchedModel.IssueWidth; } in getIssueWidth()
99 unsigned IssueWidth; variable
139 unsigned IssueWidth; member
40 let IssueWidth = 1;
50 let IssueWidth = 1;
162 let IssueWidth = 1; // 1 instruction is dispatched per cycle.
120 let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle.
313 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
163 let IssueWidth = 4;
199 let IssueWidth = 4;
303 let IssueWidth = 4;
21 let IssueWidth = 5; // 5-wide issue for expanded uops
18 let IssueWidth = 2;
19 let IssueWidth = 4;
623 // IssueWidth is analogous to the number of decode units. Core and its641 let IssueWidth = 4;
19 let IssueWidth = 2;
90 // global IssueWidth property, which constrains the number of microops
80 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.284 // against the processor's IssueWidth limit. If an instruction can