Searched refs:SMRD (Results 1 – 13 of 13) sorted by relevance
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | smrd.ll | 5 ; SMRD load with an immediate offset.
17 ; SMRD load with the largest possible immediate offset.
29 ; SMRD load with an offset greater than the largest possible immediate.
44 ; SMRD load with a 64-bit offset
59 ; SMRD load with the largest possible immediate offset on VI
73 ; SMRD load with an offset greater than the largest possible immediate on VI
87 ; SMRD load using the load.const intrinsic with an immediate offset
100 ; SMRD load using the load.const intrinsic with the largest possible immediate
113 ; SMRD load using the load.const intrinsic with an offset greater than the
130 ; SMRD load with the largest possible immediate offset on VI
[all …]
|
| D | salu-to-valu.ll | 53 ; Test moving an SMRD instruction to the VALU
90 ; Test moving an SMRD with an immediate offset to the VALU
106 ; Use a big offset that will use the SMRD literal offset on CI
|
| D | si-sgpr-spill.ll | 22 ; Writing to M0 from an SMRD instruction will hang the GPU.
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | GCNHazardRecognizer.cpp | 197 int GCNHazardRecognizer::checkSMRDHazards(MachineInstr *SMRD) { in checkSMRDHazards() argument
202 WaitStatesNeeded = checkSMEMSoftClauseHazards(SMRD); in checkSMRDHazards()
213 for (const MachineOperand &Use : SMRD->uses()) { in checkSMRDHazards()
|
| D | GCNHazardRecognizer.h | 43 int checkSMRDHazards(MachineInstr *SMRD);
|
| D | SIInstrInfo.h | 296 return MI.getDesc().TSFlags & SIInstrFlags::SMRD; in isSMRD()
300 return get(Opcode).TSFlags & SIInstrFlags::SMRD; in isSMRD()
360 return MI.getDesc().TSFlags & (SIInstrFlags::SALU | SIInstrFlags::SMRD); in isScalarUnit()
|
| D | SIInstrFormats.td | 40 field bits<1> SMRD = 0;
76 let TSFlags{18} = SMRD;
345 class SMRD <dag outs, dag ins, string asm, list<dag> pattern> :
349 let SMRD = 1;
|
| D | SIDefines.h | 37 SMRD = 1 << 18, enumerator
|
| D | CIInstructions.td | 93 // SMRD Instructions
|
| D | SIInstructions.td | 41 // SMRD Instructions
45 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
46 // and writing to M0 from an SMRD instruction will hang the GPU.
2361 // SMRD Patterns
2369 (vt (!cast<SMRD>(Instr#"_IMM") $sbase, $offset))
2375 (vt (!cast<SMRD>(Instr#"_SGPR") $sbase, $offset))
2380 (vt (!cast<SMRD>(Instr#"_IMM_ci") $sbase, $offset))
2386 // Global and constant loads can be selected to either MUBUF or SMRD
2387 // instructions, but SMRD instructions are faster so we want the instruction
|
| D | SIRegisterInfo.td | 256 // Subset of SReg_32 without M0 for SMRD instructions and alike.
|
| D | SIInstrInfo.td | 77 // Specify an SMRD opcode for SI and SMEM opcode for VI
986 // SMRD classes
990 SMRD <outs, ins, "", pattern>,
998 SMRD <outs, ins, asm, []>,
1008 SMRD <outs, ins, asm, []>,
1019 SMRD <outs, ins, asm, pattern>,
1029 SMRD <outs, ins, asm, pattern>,
1119 def _IMM_ci : SMRD <
|
| /external/llvm/docs/ |
| D | AMDGPUUsage.rst | 59 SMRD Instructions
61 Only the s_load_dword* SMRD instructions are supported.
|