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Searched refs:VLD4DUP (Results 1 – 8 of 8) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMISelLowering.h193 VLD4DUP, enumerator
DARMInstrNEON.td1037 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1038 class VLD4DUP<bits<4> op7_4, string Dt>
1048 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1049 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1050 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1057 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1058 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1059 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
DARMISelLowering.cpp924 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
7216 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
7304 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
7957 case ARMISD::VLD4DUP: in PerformDAGCombine()
DARMISelDAGToDAG.cpp2729 case ARMISD::VLD4DUP: { in Select()
/external/llvm/lib/Target/ARM/
DARMISelLowering.h195 VLD4DUP, enumerator
DARMInstrNEON.td1560 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1561 class VLD4DUP<bits<4> op7_4, string Dt>
1571 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1572 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1573 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1580 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1581 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1582 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
DARMISelLowering.cpp1229 case ARMISD::VLD4DUP: return "ARMISD::VLD4DUP"; in getTargetNodeName()
9963 case ARMISD::VLD4DUP: NewOpc = ARMISD::VLD4DUP_UPD; NumVecs = 4; break; in CombineBaseUpdate()
10134 NewOpc = ARMISD::VLD4DUP; in CombineVLDDUP()
11066 case ARMISD::VLD4DUP: in PerformDAGCombine()
DARMISelDAGToDAG.cpp3163 case ARMISD::VLD4DUP: { in Select()