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Searched refs:getNumDefs (Results 1 – 25 of 57) sorted by relevance

123

/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/
DBlackfinISelDAGToDAG.cpp154 if (UI.getUse().getResNo() >= DefMCID.getNumDefs()) in FixRegisterClasses()
160 if (UseMCID.getNumDefs()+UI.getOperandNo() >= UseMCID.getNumOperands()) in FixRegisterClasses()
163 TII.getRegClass(UseMCID, UseMCID.getNumDefs()+UI.getOperandNo(), TRI); in FixRegisterClasses()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp117 if (i+II.getNumDefs() < II.getNumOperands()) in EmitCopyFromReg()
118 RC = TII->getRegClass(II, i+II.getNumDefs(), TRI); in EmitCopyFromReg()
194 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
688 bool HasPhysRegOuts = NumResults > II.getNumDefs() && II.getImplicitDefs()!=0; in EmitMachineNode()
737 bool HasOptPRefs = II.getNumDefs() > NumResults; in EmitMachineNode()
740 unsigned NumSkip = HasOptPRefs ? II.getNumDefs() - NumResults : 0; in EmitMachineNode()
742 AddOperand(MI, Node->getOperand(i), i-NumSkip+II.getNumDefs(), &II, in EmitMachineNode()
756 for (unsigned i = II.getNumDefs(); i < NumResults; ++i) { in EmitMachineNode()
757 unsigned Reg = II.getImplicitDefs()[i - II.getNumDefs()]; in EmitMachineNode()
774 for (unsigned i = NumResults, e = II.getNumDefs()+II.getNumImplicitDefs(); in EmitMachineNode()
[all …]
DFastISel.cpp1117 if (II.getNumDefs() >= 1) in FastEmitInst_r()
1137 if (II.getNumDefs() >= 1) in FastEmitInst_rr()
1159 if (II.getNumDefs() >= 1) in FastEmitInst_rrr()
1182 if (II.getNumDefs() >= 1) in FastEmitInst_ri()
1203 if (II.getNumDefs() >= 1) in FastEmitInst_rii()
1226 if (II.getNumDefs() >= 1) in FastEmitInst_rf()
1248 if (II.getNumDefs() >= 1) in FastEmitInst_rri()
1270 if (II.getNumDefs() >= 1) in FastEmitInst_i()
1286 if (II.getNumDefs() >= 1) in FastEmitInst_ii()
DScheduleDAGSDNodes.cpp116 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
117 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) { in CheckForPhysRegDependency()
413 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
503 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
590 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in ComputeOperandLatency()
DScheduleDAGRRList.cpp1029 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1863 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
1910 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2040 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in UnscheduledNode()
2057 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in UnscheduledNode()
2610 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2663 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
2827 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h338 operands_begin() + getDesc().getNumDefs());
343 operands_begin() + getDesc().getNumDefs());
348 return make_range(operands_begin() + getDesc().getNumDefs(),
353 return make_range(operands_begin() + getDesc().getNumDefs(),
357 return make_range(operands_begin() + getDesc().getNumDefs(),
361 return make_range(operands_begin() + getDesc().getNumDefs(),
/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp1821 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_r()
1823 if (II.getNumDefs() >= 1) in fastEmitInst_r()
1843 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rr()
1844 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rr()
1846 if (II.getNumDefs() >= 1) in fastEmitInst_rr()
1868 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_rrr()
1869 Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1); in fastEmitInst_rrr()
1870 Op2 = constrainOperandRegClass(II, Op2, II.getNumDefs() + 2); in fastEmitInst_rrr()
1872 if (II.getNumDefs() >= 1) in fastEmitInst_rrr()
1894 Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs()); in fastEmitInst_ri()
[all …]
DScheduleDAGSDNodes.cpp127 if (ResNo >= II.getNumDefs() && in CheckForPhysRegDependency()
128 II.ImplicitDefs[ResNo - II.getNumDefs()] == Reg) in CheckForPhysRegDependency()
451 if (NumUsed > TII->get(N->getMachineOpcode()).getNumDefs()) in AddSchedEdges()
550 unsigned NRegDefs = SchedDAG->TII->get(Node->getMachineOpcode()).getNumDefs(); in InitNodeNumDefs()
637 OpIdx += TII->get(Use->getMachineOpcode()).getNumDefs(); in computeOperandLatency()
DInstrEmitter.cpp135 if (i+II.getNumDefs() < II.getNumOperands()) { in EmitCopyFromReg()
137 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF)); in EmitCopyFromReg()
216 for (unsigned i = 0; i < II.getNumDefs(); ++i) { in CreateVirtualRegisters()
753 unsigned NumDefs = II.getNumDefs(); in EmitMachineNode()
DScheduleDAGRRList.cpp1198 NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1973 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in MayReduceRegPressure()
2019 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in RegPressureDiff()
2147 unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2164 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in unscheduledNode()
2676 unsigned NumRes = MCID.getNumDefs(); in canClobber()
2733 unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs(); in canClobberPhysRegDefs()
2898 unsigned NumRes = MCID.getNumDefs(); in AddPseudoTwoAddrDeps()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DExecutionDepsFix.cpp313 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
323 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
342 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
441 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitGenericInstr()
DPeepholeOptimizer.cpp269 unsigned NumDefs = MI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
299 NumDefs = DefMI->getDesc().getNumDefs(); in OptimizeBitcastInstr()
358 if (MCID.getNumDefs() != 1) in isMoveImmediate()
DTargetInstrInfoImpl.cpp63 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
129 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
/external/llvm/lib/Target/WebAssembly/InstPrinter/
DWebAssemblyInstPrinter.cpp147 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
154 if (OpNo < MII.get(MI->getOpcode()).getNumDefs()) in printOperand()
/external/llvm/lib/CodeGen/
DPeepholeOptimizer.cpp375 assert(DefIdx < Def->getDesc().getNumDefs() && in ValueTracker()
892 NumDefs = MI.getDesc().getNumDefs(); in UncoalescableRewriter()
1186 assert(MI->getDesc().getNumDefs() == 1 && in optimizeCoalescableCopy()
1300 if (MCID.getNumDefs() != 1) in isLoadFoldable()
1322 if (MCID.getNumDefs() != 1) in isMoveImmediate()
1626 for (unsigned i = MIDesc.getNumDefs(); i != MIDesc.getNumOperands(); in runOnMachineFunction()
1689 if (Def->getDesc().getNumDefs() != 1) in getNextSourceFromBitcast()
1890 (DefIdx < Def->getDesc().getNumDefs() || in getNextSourceImpl()
DExecutionDepsFix.cpp518 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs(); in processDefs()
590 for (unsigned i = mi->getDesc().getNumDefs(), in visitHardInstr()
600 for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) { in visitHardInstr()
619 for (unsigned i = mi->getDesc().getNumDefs(), in visitSoftInstr()
DImplicitNullChecks.cpp430 Offset < PageSize && MI.getDesc().getNumDefs() <= 1 && in analyzeBlockForNullChecks()
492 unsigned NumDefs = LoadMI->getDesc().getNumDefs(); in insertFaultingLoad()
DDetectDeadLanes.cpp284 if (MI.getDesc().getNumDefs() != 1) in transferDefinedLanesStep()
432 assert(UseMI.getDesc().getNumDefs() == 1); in determineInitialUsedLanes()
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCChecker.cpp62 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
116 for (unsigned i = 0; i < MCID.getNumDefs(); ++i) { in init()
204 for (unsigned i = MCID.getNumDefs(); i < MCID.getNumOperands(); ++i) in init()
/external/llvm/lib/Target/AArch64/
DAArch64DeadRegisterDefinitionsPass.cpp102 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) { in processMachineBasicBlock()
DAArch64FastISel.cpp1062 constrainOperandRegClass(II, Addr.getReg(), II.getNumDefs()+Idx)); in addLoadStoreOperands()
1064 constrainOperandRegClass(II, Addr.getOffsetReg(), II.getNumDefs()+Idx+1)); in addLoadStoreOperands()
1261 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rr()
1262 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rr()
1306 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_ri()
1346 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rs()
1347 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rs()
1389 LHSReg = constrainOperandRegClass(II, LHSReg, II.getNumDefs()); in emitAddSub_rx()
1390 RHSReg = constrainOperandRegClass(II, RHSReg, II.getNumDefs() + 1); in emitAddSub_rx()
2060 SrcReg = constrainOperandRegClass(II, SrcReg, II.getNumDefs()); in emitStore()
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h183 unsigned getNumDefs() const { in getNumDefs() function
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMFastISel.cpp293 if (II.getNumDefs() >= 1) in FastEmitInst_r()
313 if (II.getNumDefs() >= 1) in FastEmitInst_rr()
336 if (II.getNumDefs() >= 1) in FastEmitInst_rrr()
360 if (II.getNumDefs() >= 1) in FastEmitInst_ri()
382 if (II.getNumDefs() >= 1) in FastEmitInst_rf()
405 if (II.getNumDefs() >= 1) in FastEmitInst_rri()
428 if (II.getNumDefs() >= 1) in FastEmitInst_i()
447 if (II.getNumDefs() >= 1) in FastEmitInst_ii()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h191 unsigned getNumDefs() const { return NumDefs; } in getNumDefs() function
/external/llvm/lib/Target/AMDGPU/AsmParser/
DAMDGPUAsmParser.cpp2179 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtMIMG()
2212 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtMIMGAtomic()
2394 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtId()
2414 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtVOP3()
2589 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtDPP()
2696 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) { in cvtSDWA()

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