1 //==-- AArch64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --==//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
13
14 #include "AArch64.h"
15 #include "AArch64RegisterInfo.h"
16 #include "llvm/ADT/Statistic.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/Target/TargetSubtargetInfo.h"
23 using namespace llvm;
24
25 #define DEBUG_TYPE "aarch64-dead-defs"
26
27 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28
29 namespace llvm {
30 void initializeAArch64DeadRegisterDefinitionsPass(PassRegistry &);
31 }
32
33 #define AARCH64_DEAD_REG_DEF_NAME "AArch64 Dead register definitions"
34
35 namespace {
36 class AArch64DeadRegisterDefinitions : public MachineFunctionPass {
37 private:
38 const TargetRegisterInfo *TRI;
39 bool implicitlyDefinesOverlappingReg(unsigned Reg, const MachineInstr &MI);
40 bool processMachineBasicBlock(MachineBasicBlock &MBB);
41 bool usesFrameIndex(const MachineInstr &MI);
42 public:
43 static char ID; // Pass identification, replacement for typeid.
AArch64DeadRegisterDefinitions()44 explicit AArch64DeadRegisterDefinitions() : MachineFunctionPass(ID) {
45 initializeAArch64DeadRegisterDefinitionsPass(
46 *PassRegistry::getPassRegistry());
47 }
48
49 bool runOnMachineFunction(MachineFunction &F) override;
50
getRequiredProperties() const51 MachineFunctionProperties getRequiredProperties() const override {
52 return MachineFunctionProperties().set(
53 MachineFunctionProperties::Property::AllVRegsAllocated);
54 }
55
getPassName() const56 const char *getPassName() const override { return AARCH64_DEAD_REG_DEF_NAME; }
57
getAnalysisUsage(AnalysisUsage & AU) const58 void getAnalysisUsage(AnalysisUsage &AU) const override {
59 AU.setPreservesCFG();
60 MachineFunctionPass::getAnalysisUsage(AU);
61 }
62 };
63 char AArch64DeadRegisterDefinitions::ID = 0;
64 } // end anonymous namespace
65
66 INITIALIZE_PASS(AArch64DeadRegisterDefinitions, "aarch64-dead-defs",
67 AARCH64_DEAD_REG_DEF_NAME, false, false)
68
implicitlyDefinesOverlappingReg(unsigned Reg,const MachineInstr & MI)69 bool AArch64DeadRegisterDefinitions::implicitlyDefinesOverlappingReg(
70 unsigned Reg, const MachineInstr &MI) {
71 for (const MachineOperand &MO : MI.implicit_operands())
72 if (MO.isReg() && MO.isDef())
73 if (TRI->regsOverlap(Reg, MO.getReg()))
74 return true;
75 return false;
76 }
77
usesFrameIndex(const MachineInstr & MI)78 bool AArch64DeadRegisterDefinitions::usesFrameIndex(const MachineInstr &MI) {
79 for (const MachineOperand &Op : MI.uses())
80 if (Op.isFI())
81 return true;
82 return false;
83 }
84
processMachineBasicBlock(MachineBasicBlock & MBB)85 bool AArch64DeadRegisterDefinitions::processMachineBasicBlock(
86 MachineBasicBlock &MBB) {
87 bool Changed = false;
88 for (MachineInstr &MI : MBB) {
89 if (usesFrameIndex(MI)) {
90 // We need to skip this instruction because while it appears to have a
91 // dead def it uses a frame index which might expand into a multi
92 // instruction sequence during EPI.
93 DEBUG(dbgs() << " Ignoring, operand is frame index\n");
94 continue;
95 }
96 if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
97 // It is not allowed to write to the same register (not even the zero
98 // register) twice in a single instruction.
99 DEBUG(dbgs() << " Ignoring, XZR or WZR already used by the instruction\n");
100 continue;
101 }
102 for (int i = 0, e = MI.getDesc().getNumDefs(); i != e; ++i) {
103 MachineOperand &MO = MI.getOperand(i);
104 if (MO.isReg() && MO.isDead() && MO.isDef()) {
105 assert(!MO.isImplicit() && "Unexpected implicit def!");
106 DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
107 MI.print(dbgs()));
108 // Be careful not to change the register if it's a tied operand.
109 if (MI.isRegTiedToUseOperand(i)) {
110 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
111 continue;
112 }
113 // Don't change the register if there's an implicit def of a subreg or
114 // superreg.
115 if (implicitlyDefinesOverlappingReg(MO.getReg(), MI)) {
116 DEBUG(dbgs() << " Ignoring, implicitly defines overlap reg.\n");
117 continue;
118 }
119 // Make sure the instruction take a register class that contains
120 // the zero register and replace it if so.
121 unsigned NewReg;
122 switch (MI.getDesc().OpInfo[i].RegClass) {
123 default:
124 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
125 continue;
126 case AArch64::GPR32RegClassID:
127 NewReg = AArch64::WZR;
128 break;
129 case AArch64::GPR64RegClassID:
130 NewReg = AArch64::XZR;
131 break;
132 }
133 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
134 MO.setReg(NewReg);
135 DEBUG(MI.print(dbgs()));
136 ++NumDeadDefsReplaced;
137 // Only replace one dead register, see check for zero register above.
138 break;
139 }
140 }
141 }
142 return Changed;
143 }
144
145 // Scan the function for instructions that have a dead definition of a
146 // register. Replace that register with the zero register when possible.
runOnMachineFunction(MachineFunction & MF)147 bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) {
148 TRI = MF.getSubtarget().getRegisterInfo();
149 bool Changed = false;
150 DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n");
151
152 if (skipFunction(*MF.getFunction()))
153 return false;
154
155 for (auto &MBB : MF)
156 if (processMachineBasicBlock(MBB))
157 Changed = true;
158 return Changed;
159 }
160
createAArch64DeadRegisterDefinitions()161 FunctionPass *llvm::createAArch64DeadRegisterDefinitions() {
162 return new AArch64DeadRegisterDefinitions();
163 }
164