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Searched refs:isOptionalDef (Results 1 – 18 of 18) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/MC/
DMCInstrDesc.h84 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
/external/llvm/include/llvm/MC/
DMCInstrDesc.h85 bool isOptionalDef() const { return Flags & (1 << MCOI::OptionalDef); } in isOptionalDef() function
/external/llvm/lib/CodeGen/
DTargetSchedule.cpp212 && !DefMI->getDesc().OpInfo[DefOperIdx].isOptionalDef() in computeOperandLatency()
DMachineVerifier.cpp900 else if (!MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
910 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
DMachineInstr.cpp1802 if (MCOI.isOptionalDef()) in print()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp1333 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitMulFrmInstruction()
1370 !MCID.OpInfo[OpIdx].isOptionalDef()) in emitExtendInstruction()
1399 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitMiscArithInstruction()
1613 MCID.OpInfo[OpIdx].isOptionalDef()) { in emitVFPArithInstruction()
DThumb2SizeReduction.cpp657 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
747 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
DARMISelLowering.cpp6334 if (!MCID.hasOptionalDef() || !MCID.OpInfo[ccOutIdx].isOptionalDef()) { in AdjustInstrPostInstrSelection()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp795 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
890 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceToNarrow()
DARMISelLowering.cpp8546 if (!MI.hasOptionalDef() || !MCID->OpInfo[ccOutIdx].isOptionalDef()) { in AdjustInstrPostInstrSelection()
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp200 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters()
287 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp236 if (II.OpInfo[i].isOptionalDef()) { in CreateVirtualRegisters()
326 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineVerifier.cpp610 if (MO->isDef() && !MCOI.isOptionalDef()) in visitMachineOperand()
DMachineInstr.cpp1449 if (MCOI.isOptionalDef()) in print()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp4370 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp571 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
/external/llvm/lib/Target/ARM/Disassembler/
DARMDisassembler.cpp579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { in AddThumb1SBit()
/external/llvm/lib/Target/ARM/AsmParser/
DARMAsmParser.cpp8761 !MCID.OpInfo[OpNo].isOptionalDef() && OpNo < MCID.NumOperands; in checkTargetMatchPredicate()